基于ice40 FPGA的Yosys优化外环振荡器

Question

我试图用ice40 (0.7)实现一个简单的yosys环形振荡器，如下所示：

module ringosc(input clkin,
               output out);

   (* keep="true" *)
   wire [100:0]              ring;

   assign ring[100:1] = ~ring[99:0];
   assign ring[0]     = ~ring[100];

   assign out = ring[0];

endmodule

然而，即使我使用的是keep属性，它似乎也得到了优化。我可以在yosys的日志输出中看到这一点：

7.14.2. Executing OPT_EXPR pass (perform const folding).
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$292' (double_invert) in module `\lfsr' with constant driver `\trng.ring [62] = \trng.ring [60]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$293' (double_invert) in module `\lfsr' with constant driver `\trng.ring [63] = \trng.ring [59]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$294' (double_invert) in module `\lfsr' with constant driver `\trng.ring [64] = \trng.ring [58]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$295' (double_invert) in module `\lfsr' with constant driver `\trng.ring [65] = \trng.ring [57]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$296' (double_invert) in module `\lfsr' with constant driver `\trng.ring [66] = \trng.ring [56]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$297' (double_invert) in module `\lfsr' with constant driver `\trng.ring [67] = \trng.ring [55]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$298' (double_invert) in module `\lfsr' with constant driver `\trng.ring [68] = \trng.ring [54]'.
...

我怎样才能阻止yosys这样做？

Answer 1

手动实例化逻辑单元，就像在这个示例项目中所做的那样：http://svn.clifford.at/handicraft/2015/ringosc/

(这个项目来自我在2015年拍摄的视频：

https://www.youtube.com/watch?v=UFqWjZudOho)