vhdl环形计数器复用器的数字电路方案

Question

我有一个电路，我想用vhdl实现。有一个时钟输入和哪个时钟事件按顺序更改1引脚输出。0001 -> 0010 -> 0100 -> 1000

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我想知道怎样才是正确的做法。我可以用多个ifs和elsifs以及一个整数计数器信号来完成这个任务。很抱歉问这个问题，这种电路有名字吗？

Answer 1

从你的描述来看，这似乎是一个环形计数器。你的门似乎多余：

library ieee;
use ieee.std_logic_1164.all;

entity ring_counter is
    port (
        clk:    in  std_logic;
        q:      out std_logic_vector (0 to 3)
    );
end entity;

architecture your_representation of ring_counter is
    signal qint: std_logic_vector (0 to 3) := "0000";
    signal all_zero:        std_logic;
begin
YOURS:
    process(clk)
    begin
        if rising_edge(clk) then
            qint(0) <= qint(3);
            qint(1) <= all_zero or qint(0);
            qint (2 to 3) <= qint(1 to 2);
        end if;
    end process;

    all_zero <= '1' when qint = "0000" else
                '0';

    q <= (qint(0) or all_zero) & qint(1 to 3);
end architecture;

有一个测试台：

library ieee;
use ieee.std_logic_1164.all;

entity ring_counter_tb is
end entity;

architecture foo of ring_counter_tb is
    signal clk:     std_logic := '0';
    signal q:       std_logic_vector(0 to 3);
begin
DUT:
    entity work.ring_counter(your_representation)
        port map (
            clk => clk,
            q => q
        );
CLOCK:
    process
    begin
        wait for 10 ns;
        clk <= not clk;
        if Now > 200 ns then
            wait;
        end if;
    end process;

end architecture;

给予：

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而经典的戒指计数器：

architecture classic of ring_counter is
    signal qint: std_logic_vector (0 to 3) := "1000";
begin
RING_CTR:
    process(clk)
    begin
        if rising_edge(clk) then
            qint <= qint(3) & qint(0 to 2);
        end if;
    end process;

    q <= qint;

end architecture;

(及改装的试验台)：

    entity work.ring_counter(classic)

给予：

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开始阶段都处于初始条件。