格子iCE40锁相环实例化出错

Question

我有256BGA封装的格子iCE40 HX8K现场可编程门阵列。我想使用可用的PLL模块之一，将外部时钟频率37 the转换为内部时钟，以便在FPGA内部使用74 the。

我在IceCube2中使用了“配置锁相环模块”，并使用了以下配置：-锁相环类型部分：-由锁相环输出驱动的GlobalNetworks : 1；-专用时钟垫；-锁相环操作模式：-无补偿模式；-附加延迟设置:否；-频率：-输入-37 the；-输出-74 the；-其他-不选择；

然后我得到了两个VHDL语言文件- SO_pll.vhd和SO_pll_inst.vhd。我有Design.vhd文件，这是我的代码应该放的地方。如果我正确理解了网格文档，我需要指定我的Design.vhd (它的实体)是顶级模块，我就是这么做的。我需要在IceCube2的设计文件列表中包含SO_pll.vhd，我做到了。最后，我需要使用SO_pll_inst.vhd中提供的模板，通过将锁相环信号映射到Design.vhd中的信号，在我的主代码中实例化锁相环。麻烦来了--怎么做呢？

---Design.vhd---

library IEEE;
use IEEE.std_logic_1164.all;

entity Design is
port(
      I_CLK: in std_logic
    );
end entity Design;


    architecture RTL of Design is

signal S_CLK : std_logic;
signal S_RESET : std_logic;

begin

SO_pll_inst: SO_pll
port map(
          REFERENCECLK => I_CLK,
          PLLOUTCORE => open,
          PLLOUTGLOBAL => S_CLK,
          RESET => S_RESET
        );

end RTL;


    ---SO_pll_inst.vhd---Generated by IceCube2

    SO_pll_inst: SO_pll
    port map(
          REFERENCECLK => ,
          PLLOUTCORE => ,
          PLLOUTGLOBAL => ,
          RESET => 
            );



---SO_pll.vhd---Generated by IceCube2
library IEEE;
use IEEE.std_logic_1164.all;

entity SO_pll is
port(
      REFERENCECLK: in std_logic;
      RESET: in std_logic;
      PLLOUTCORE: out std_logic;
      PLLOUTGLOBAL: out std_logic
    );
end entity SO_pll;

architecture BEHAVIOR of SO_pll is
signal openwire : std_logic;
signal openwirebus : std_logic_vector (7 downto 0);
component SB_PLL40_CORE
  generic (
        --- Feedback
FEEDBACK_PATH : string := "SIMPLE"; -- String (simple, delay, 
phase_and_delay, external)
DELAY_ADJUSTMENT_MODE_FEEDBACK   : string := "FIXED"; 
DELAY_ADJUSTMENT_MODE_RELATIVE   : string := "FIXED"; 
SHIFTREG_DIV_MODE : bit_vector(1 downto 0)  := "00"; 
--  0-->Divide by 4, 1-->Divide by 7, 3 -->Divide by 5  
FDA_FEEDBACK    : bit_vector(3 downto 0)    := "0000"; 
--  Integer (0-15). 
FDA_RELATIVE    : bit_vector(3 downto 0)    := "0000";  
--  Integer (0-15).
PLLOUT_SELECT   : string := "GENCLK";

--- Use the spread sheet to populate the values below
DIVF    : bit_vector(6 downto 0); 
-- Determine a good default value
DIVR    : bit_vector(3 downto 0);
-- Determine a good default value
DIVQ    : bit_vector(2 downto 0);
-- Determine a good default value
FILTER_RANGE    : bit_vector(2 downto 0);
-- Determine a good default value

--- Additional C-Bits
ENABLE_ICEGATE  : bit := '0';

--- Test Mode Parameter 
TEST_MODE   : bit := '0';
EXTERNAL_DIVIDE_FACTOR  : integer := 1
-- Not Used by model, Added for PLL config GUI
   );
port (
    REFERENCECLK    : in std_logic;    -- Driven by core logic
    PLLOUTCORE  : out std_logic;   -- PLL output to core logic
    PLLOUTGLOBAL    : out std_logic;   -- PLL output to global network
    EXTFEEDBACK : in std_logic;    -- Driven by core logic
    DYNAMICDELAY    : in std_logic_vector (7 downto 0); -- Driven by core 
logic
    LOCK        : out std_logic;    -- Output of PLL
    BYPASS      : in std_logic;     -- Driven by core logic
    RESETB      : in std_logic;     -- Driven by core logic
    LATCHINPUTVALUE : in std_logic;     -- iCEGate Signal
    -- Test Pins
    SDO     : out std_logic;    -- Output of PLL
    SDI     : in std_logic;     -- Driven by core logic
    SCLK        : in std_logic      -- Driven by core logic
   );
end component;
begin
SO_pll_inst: SB_PLL40_CORE
-- Fin=37, Fout=74
generic map(
         DIVR => "0000",
         DIVF => "0001111",
         DIVQ => "011",
         FILTER_RANGE => "011",
         FEEDBACK_PATH => "SIMPLE",
         DELAY_ADJUSTMENT_MODE_FEEDBACK => "FIXED",
         FDA_FEEDBACK => "0000",
         DELAY_ADJUSTMENT_MODE_RELATIVE => "FIXED",
         FDA_RELATIVE => "0000",
         SHIFTREG_DIV_MODE => "00",
         PLLOUT_SELECT => "GENCLK",
         ENABLE_ICEGATE => '0'
       )
port map(
      REFERENCECLK => REFERENCECLK,
      PLLOUTCORE => PLLOUTCORE,
      PLLOUTGLOBAL => PLLOUTGLOBAL,
      EXTFEEDBACK => openwire,
      DYNAMICDELAY => openwirebus,
      RESETB => RESET,
      BYPASS => '0',
      LATCHINPUTVALUE => openwire,
      LOCK => open,
      SDI => openwire,
      SDO => open,
      SCLK => openwire
    );

end BEHAVIOR;

我刚刚将Design.vhd和SO_pll.vhd添加到设计文件列表中。如果我用Lattice LSE运行综合，合成是成功的，但placer报告显示使用了0/2 PLL。如果我用Synplify Pro placer运行Synthesys，报告显示使用了1/2 PLL，但我真的不能使用它，因为我没有映射信号。

当我从SO_pll_inst.vhd中获取模板并将其放入Design.vhd的体系结构中时，我得到了错误消息："ERROR -综合: design.vhd(19)：so_pll未声明。“好吧，显然我遗漏了一些东西。如果它是一个模板，我希望只映射我的信号并让它运行。但不是。不是我做错了什么，就是……我做错了什么:)请帮帮忙。

Answer 1

有趣-我发布了这个问题，我正在发布答案！:)它是这样的：

---Design.vhd---

library IEEE;
use IEEE.std_logic_1164.all;

entity Design is
port(
      I_CLK: in std_logic;
      I_RESET: in std_logic;
      O_PLLOUTGLOBAL : out std_logic
    );
end entity Design;

architecture RTL of Design is

begin

SO_pll_inst: entity SO_pll
port map(
          REFERENCECLK => I_CLK,
          PLLOUTCORE => open,
          PLLOUTGLOBAL => O_PLLOUTGLOBAL,
          RESET => I_RESET
        );

end RTL;

因此，从上面的文件中可以明显看出，关键在于PLL文件实体的实例化。我在PLL文件中指定的实体名称之前缺少关键字" entity“。不出所料，我做错了什么。