VHDL代码综合错误

Question

我已经写了一个VHDL代码来实现PWM控制器的功能。我已经成功地对其进行了模拟，结果与预期一致。我还检查了合成的语法，但它没有显示任何错误。当我使用XILINX ISE 12.4进行综合时，它不能综合，并且错误状态

错误:Xst:827-第67行:无法合成信号tmp_PC，同步描述错误。当前软件版本不支持用于描述同步元素(寄存器、内存等)的描述样式。

--library UNISIM;
--use UNISIM.VComponents.all;

entity CONTROLLER is
PORT(

    CLK:    IN  STD_LOGIC;
    VOUT: IN  STD_LOGIC;
    M1:   OUT STD_LOGIC:='0';
    M2:   OUT STD_LOGIC:='0'

);


end CONTROLLER;

architecture Behavioral of CONTROLLER is

    SIGNAL VREF:        STD_LOGIC_VECTOR(7 DOWNTO 0):="01000000";
    SIGNAL V_ERR:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL PWM:         STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL PWM_NEW:         STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL COUNT:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL COUNT2:          STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL TEMP1:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL TEMP2:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL TEMP3:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL FEED_BACK:       STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL REG:         STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL PWM_COUNT:       STD_LOGIC_VECTOR(7 DOWNTO 0):="10000000";

BEGIN

PROCESS(CLK)

BEGIN

    IF(RISING_EDGE(CLK) AND COUNT2<"10000000")THEN
            COUNT <= COUNT+'1';
    END IF;

    IF(RISING_EDGE(CLK) AND COUNT2>="10000000")THEN
        COUNT <= COUNT+'1';
    END IF;

    IF (COUNT>"00000101" AND COUNT<"01111000") THEN
        IF(RISING_EDGE(CLK))THEN
            IF (VOUT='0') THEN
                FEED_BACK<= FEED_BACK+'1';
            END IF;
        END IF;
    END IF;   

    IF (COUNT>"01111000" AND COUNT<"01111100")THEN
        REG<=FEED_BACK;
        TEMP1<=VREF-REG;
        IF(TEMP1>"01000000") THEN
           TEMP2<=TEMP1+"11111111";
            V_ERR<=TEMP2+'1';
        END IF;
        IF (TEMP1<"01000000") THEN
                V_ERR<=TEMP1;
        END IF;

        PWM<=V_ERR+VREF;

        IF (PWM>"11000000")THEN
             PWM<="11000000";
        IF(PWM<"00001010")THEN
            PWM<="00001010";

        END IF;
        END IF;

    END IF;

    PWM_NEW<= PWM;

   IF (RISING_EDGE(CLK))THEN
        IF(COUNT="01111111")THEN
            COUNT<="00000000";
            FEED_BACK<="00000000";
        END IF;
    END IF;

    IF(RISING_EDGE(CLK))THEN
        COUNT2 <= COUNT2+ '1';
    END IF;

   IF(COUNT>"00000000" AND COUNT<("00000010"))THEN
        IF(RISING_EDGE(CLK)) THEN
            M1<='0';
            M2<='0';
        END IF;
   END IF;

    IF(COUNT>("00000010") AND COUNT<("00000010"+PWM_NEW))THEN
        IF(RISING_EDGE(CLK)) THEN
            M1<='1';
            M2<='0';
        END IF;
   END IF;

    IF(COUNT>("00000010"+PWM_NEW) AND COUNT<("00000100"+PWM_NEW))THEN
        IF ( RISING_EDGE(CLK)) THEN
            M1<='0';
            M2<='0';
        END IF;
    END IF;

    IF(COUNT>("00000100"+PWM_NEW) AND COUNT<("10000000"))THEN
        IF (RISING_EDGE(CLK)) THEN
            M1<='0';
            M2<='1';
        END IF;
    END IF;

    IF (COUNT=("10000000"))THEN
        IF (RISING_EDGE(CLK)) THEN
            COUNT2<="10000001";
        END IF;
    END IF;

END PROCESS;
end Behavioral;`

我尝试查找错误消息，得到了不同的答案。可能的原因看起来是1:不适当的"IF“嵌套，这不是根据合成模板。2:使用"risisng_edge(clk)“代替通常的”(clk‘’event and clk='1')“。

我仍然不能完全确定到底是什么问题。如果有人能建议我忽略的可能的错误，那将是非常有帮助的。

Answer 1

为了被合成工具识别，您的进程必须具有single if rising_edge(clk)块。

调整代码应该很容易，但使用reg <= feed_back;的代码块除外

如果此特定部分对异步行为进行建模，则将其移动到组合流程。

考虑到可能的原因1.和2.你列出的，你的代码在这两个方面都是正常的:嵌套是正常的(语法上)，你对rising_edge的使用也是正常的。

Answer 2

看起来你可以做你的代码完全同步

process(clk)
begin
    -- put your asyncron code here if needed
    if(rising_edge(clk)) then
      if(reset = '1') then
      -- if you like to implement a synchron reset
      else
      -- all your synchron code e.g.

         if (COUNT2 >= "10000000") then
            COUNT <= COUNT+'1';
         end if;

         if (COUNT > ("00000100"+PWM_NEW)) AND (COUNT < "10000000") then
            M1 <= '0';
            M2 <= '1';
         end if;
         .
         .
         .

      end if;
   end if;
   -- put your asyncron code here if needed
end process;

不要使用unisim库...你可以用这两个来做任何事情

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

有标准化的。

为了让它更清楚一点，你可以用十六进制的文字

if (COUNT2 >= x"80") then -- 80 hex = 124 dec
   COUNT <= COUNT+'1';
end if;

或者，您可以使用无符号信号

SIGNAL COUNT:       unsigned (7 DOWNTO 0) := (others => '0'); -- same as "000000000" but looks better

if (COUNT2 >= 128) then
   COUNT <= COUNT + '1';
end if;

计算不是问题，例如

if (COUNT > ("00000100"+PWM_NEW)) AND (COUNT < "10000000") then
   M1 <= '0';
   M2 <= '1';
end if;

将会是

 if (COUNT > (unsigned(PWM_NEW) + 4)) AND (COUNT < 128) then
    M1 <= '0';
    M2 <= '1';
 end if;