XILINX ISE将I/O标记设置为时钟

Question

我在Xilinx ISE IDE上，正在使用Schematic Editor。

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约束文件如下：

NET "A" LOC = M18;
NET "F" LOC = P15;
NET "B" LOC = M16;


NET "A" PULLUP;
NET "B" PULLUP;
NET "F" DRIVE = 8;

但是当我想编译我的程序时，会出现这样的错误：

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <B> is placed at site <M16>. The corresponding BUFG component
   <B_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set
   of IOBs that can use the fast path to the Clocker buffer, and they are not
   being used. You may want to analyze why this problem exists and correct it.
   If this sub optimal condition is acceptable for this design, you may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING and allow your design to continue. However, the use of this override
   is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to override this clock rule.
   < NET "B" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

如何修复它？

Answer 1

虽然理论上任何信号都可以用作时钟，但对于FPGA却并非如此；至少在最佳情况下不是这样。时钟需要特殊的考虑，这些考虑转化为限制FPGA的哪个引脚可以被路由到时钟网络。

我怀疑在你的例子中，你使用了一个按钮作为时钟信号，这只能在一个非常小的设计上工作(像你的)，因为去抖动和事实是它不是一个支持时钟的输入端口。

您可以通过向.ucf添加以下约束来告诉工具您想要次优或潜在错误的时钟路径：

NET "B" CLOCK_DEDICATED_ROUTE = FALSE;

请记住，您不应该在没有确保您的设计与之兼容的情况下这样做。我建议你进一步设计一个“真实的”时钟连接到你的FPGA上的时钟端口，每个板都有一个。这种限制将使您的设计工作，但在更大，更快的设计很可能是一个问题的来源。