Vhdl乘法器使用率太低

Question

我的设计使用了斯巴达3E XC35100E设备。我总共可以使用4个多路复用器。然而，尽管使用了3*符号和FFT块(也使用了3个MUX)，但设计摘要指定我只使用1个MUX。即使我使用CLB逻辑代替FFT块的MUX，设计摘要也是一样的。

实现和模拟能够进行，没有任何问题。那么，为什么我使用的多路复用器数量如此之少？任何帮助都将不胜感激。

为简洁起见，相关的库、端口映射和信号声明被排除在外。

process (clk) 
 variable fsm : integer range 0 to 3:= 0;
 variable i : integer range 0 to 127:= 0; 
begin

if rising_edge(clk) then
    if fsm = 0 then
        tasiyici <= STD_LOGIC_VECTOR(to_signed(sample_1(i)* sample_2(i) , 16));
 --sample1 and sample 2 are arrays with constant values
        fsm := fsm +1;


    elsif fsm = 1 then
        wea_select <= '0';
        wea_ram<= "1";
        ram_write <= '0';
        dina <= STD_LOGIC_VECTOR(tasiyici(15 downto 8));
        mult_out<= STD_LOGIC_VECTOR(tasiyici(15 downto 8));
        fsm := fsm +1;

    elsif fsm = 2 then
        address_write <= std_logic_vector(unsigned(addra) + 1);
        wea_ram<= "0";
        i := i+1 ;
        if i=128 then
            fsm:=3;
            ram_write <= '1';
            wea_select <= '1';
        else
            fsm := 0;
        end if;

    end if;

end if;

end process;


----FFT process---
process(clk) 
variable fsm : integer range 0 to 7:= 0;
variable i : integer range 0 to 128; 
variable counter : integer range 0 to 2:= 0;
variable j : integer range 0 to 512; 

begin
if rising_edge(clk)  then

    if fsm = 0 then  -- ram_write is control 
        if ram_write = '1' then 
            wea_fft <= "0";
            fsm:= 1;
        end if;

    elsif fsm = 1 then --process start (pulse)
        start <= '1';
        fwd_inv_we <= '1';
        fsm := fsm +1;

    elsif fsm = 2 then
            start <= '0';
            fwd_inv_we <= '0';
            fsm := fsm +1;

    elsif fsm =3 then --128 cycle send data from douta to xn_re
        if i= 128 then
            fsm := fsm +1;
        else
            xn_re <= douta;
            address_read <= std_logic_vector(unsigned(addra) + 1);
            i:=i+1;
            fsm := 3;
        end if;

     elsif fsm =4 then --all data sent. process complete
        if done = '1'  then --wait for done finish 3 clk cycle, then unload
            if counter= 2 then
                fsm := fsm +1;
            else
                counter := counter +1;
                fsm :=4;
            end if;
        end if;

    elsif fsm =5 then
        counter := 0;
        unload <= '1';
        fsm := fsm +1;
        fft_data_ready <= "1";      
        wea_fft<= "1";


    elsif fsm =6 then --wait 512 clk cycle to read all outputs
        unload <= '0';
        wea_fft<= "0";

        if dv = '1' then

  fft_output <=  std_logic_vector(signed(xk_re(15 downto 4))*signed(xk_re(15 downto 4))
                               +signed(xk_im(15 downto 4))*signed(xk_im(15 downto 4)));             
            if j=512 then 
                fsm:=fsm+1;
            else
            j:=j+1;
            fsm:=6;
            end if;
        else
            fsm:=6;
        end if;
    end if;
end if;
end process;

Answer 1

看起来你的设计已经被简单地优化了。

您应该检查合成的RTL，以检查您的设计是否按您想要的方式进行了合成