我想在SpinalHDL中创建一个三元条件,作为Verilog中的一个三元赋值:
例如:
wire my_condition = (this == that);
wire [1:0] my_ternary_wire = my_condition ? 2'b10 : 2'b01;所需的SpinalHDL代码:
val myCondition = this === that
val myTernaryWire = myCondition ? B(3) : B(1)发布于 2020-08-16 00:51:04
我刚刚看到可以使用:
val myCondition = this === that
val myTernaryWire = myCondition ? B(3) | B(1)只需将:更改为|
https://stackoverflow.com/questions/63428526
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