如何删除自动生成的YOSYS评论？

Question

当我使用YOSYS合成我的verilog代码时，生成的网表包含如下注释：(* src = "counter.v:6“*)。我想获得一个没有这些注释的网表文件。

这是我的counter.v

module counter (clk, rst, en, count);
    input clk, rst, en;
    output reg [1:0] count;

    always @(posedge clk)
        if (rst)
            count <= 2'd0;
        else if (en)
            count <= count + 2'd1;
endmodule

这是我的YOSYS脚本counter.ys

read_verilog counter.v
hierarchy -check -top counter
proc; opt; memory; opt; fsm; opt
techmap; opt
splitnets -ports;;
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean
write_verilog netlist.v

这是输出文件netlist.v

/* Generated by Yosys 0.8+576 (git sha1 dd8d264b, clang 6.0.0-1ubuntu2 -fPIC -Os) */

(* top =  1  *)
(* src = "counter.v:1" *)
module counter(clk, rst, en, \count[0] , \count[1] );
  (* src = "counter.v:6" *)
  wire _00_;
  (* src = "counter.v:6" *)
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  (* src = "counter.v:3" *)
  input clk;
  (* src = "counter.v:4" *)
  output \count[0] ;
  (* src = "counter.v:4" *)
  output \count[1] ;
  (* src = "counter.v:3" *)
  input en;
  (* src = "counter.v:3" *)
  input rst;
  NAND _11_ (
    .A(_08_),
    .B(_10_),
    .Y(_06_)
  );
  NAND _12_ (
    .A(_09_),
    .B(_06_),
    .Y(_07_)
  );
  NOR _13_ (
    .A(_05_),
    .B(_07_),
    .Y(_01_)
  );
  NOT _14_ (
    .A(\count[1] ),
    .Y(_08_)
  );
  NOT _15_ (
    .A(rst),
    .Y(_09_)
  );
  NAND _16_ (
    .A(en),
    .B(\count[0] ),
    .Y(_10_)
  );
  NOR _17_ (
    .A(en),
    .B(\count[0] ),
    .Y(_02_)
  );
  NOR _18_ (
    .A(rst),
    .B(_02_),
    .Y(_03_)
  );
  NAND _19_ (
    .A(_10_),
    .B(_03_),
    .Y(_04_)
  );
  NOT _20_ (
    .A(_04_),
    .Y(_00_)
  );
  NOR _21_ (
    .A(_08_),
    .B(_10_),
    .Y(_05_)
  );
  (* src = "counter.v:6" *)
  DFF _22_ (
    .C(clk),
    .D(_00_),
    .Q(\count[0] )
  );
  (* src = "counter.v:6" *)
  DFF _23_ (
    .C(clk),
    .D(_01_),
    .Q(\count[1] )
  );
endmodule

Answer 1

您可以使用write_verilog -noattr -这些是Verilog2001属性，而不是注释。