如何使用System Verilog编写wrap计算代码,随机约束中的参数为hsize2:0 hburst2 2:0& haddr31:0
class adddress_cal;
rand bit[31:0]haddr;
rand bit[2:0]hsize;
rand bit[2:0]hburst;
//how to write the random constraint for wrap address 发布于 2021-02-10 03:02:31
constraint addr_in_4k { haddr%4096 + (hburst + 1 << hsize) <= 4096;}https://stackoverflow.com/questions/66123100
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