SV错误:通过端口连接驱动，是多驱动的

Question

我正在尝试使用always_ff过程为下面的模型编写SV代码，但它不起作用。

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我的system-verilog代码如下：

module circuit 
(
    input clk,
    output logic reg_1, reg_2, reg_3, reg_4 ,reg_5, reg_6, reg_7, reg_8
);

logic reg4_in, reg3_in, reg2_in;

assign reg4_in = reg_5 ^ reg_1; 
assign reg3_in = reg_4 ^ reg_1; 
assign reg2_in = reg_3 ^  reg_1; 

always_ff @(posedge clk) 
begin
    {reg_1,reg_2,reg_3,reg_4,reg_5,reg_6,reg_7,reg_8} <= {reg_2,reg2_in,reg3_in,reg4_in,reg_6,reg_7,reg_8,reg_1}; 
end
endmodule

我的测试平台在这里：

module test;
  
logic clk;
logic reg_1,reg_2,reg_3,reg_4,reg_5,reg_6,reg_7,reg_8;
  
always
#5 clk = ~clk; //generation of clock

circuit U_circuit (.*); //Instantiation
    
initial begin
  $dumpfile("dump.vcd"); $dumpvars;
  
  reg_1 = 1'b1;
  reg_2 = 1'b0;
  reg_3 = 1'b0;
  reg_4 = 1'b0;
  reg_5 = 1'b0;
  reg_6 = 1'b0;
  reg_7 = 1'b0;
  reg_8 = 1'b0;
  clk = 1'b0;
  
  #100 $finish; //end of simulation
end

initial begin
$recordfile("waves.trn"); //creation of waveforms
$recordvars();
end
  
endmodule

当我试图运行模拟时，我收到了这些错误(它被重复了几次)：

>     > # ** Error (suppressible): (vsim-3839) Variable '/test/reg_8', driven via a port connection, is multiply driven. See testbench.sv(9).
>     > #    Time: 0 ns  Iteration: 0  Instance: /test File: testbench.sv Line: 21
>     > # ** Error (suppressible): (vsim-3839) Variable '/test/reg_7', driven via a port connection, is multiply driven. See testbench.sv(9).
>     > #    Time: 0 ns  Iteration: 0  Instance: /test File: testbench.sv Line: 20

更容易阅读的EDA链接：https://www.edaplayground.com/x/8KfD

Answer 1

您的测试台正在尝试对reg_1...reg_8进行过程性赋值，但它们已经由circuit模块的输出驱动。您需要添加一个重置输入。此外，您应该声明数组，而不是单独命名的信号。这使得使用它变得更容易。

module circuit 
(
    input clk, rst,
    output logic [1:8] reg_out; // 
);

logic [2:4] reg_in;

assign reg_in[4] = reg_out[5] ^ reg_out[1]; 
assign reg_in[3] = reg_out[4] ^ reg_out[1]; 
assign reg_in[2] = reg_out[3] ^ reg_out[1]; 
 
always_ff @(posedge clk or negedge rst) 
begin
    if (rst)
        reg_out = 8'b10000000
    else
       reg_out <= {reg_out[2],reg_in,reg_out[6:8],reg_outt[1]}; 
end
endmodule