我怎么做一个8位堆栈？

Question

我已经有了一个4位堆栈，但我不知道如何使它成为8位堆栈。这是一个更大的项目的一部分，我正在fpga上做一个“苏打机模拟器”(Bassy2，ISE Webpack)。到目前为止它看起来是这样的：

实现堆栈的模块：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity stack is

  port

  (
  A: in std_Logic_vector(3 downto 0);
  S_aux: in std_Logic_vector(1 downto 0);
  Q_aux: in std_Logic_vector(3 downto 0);
  clk_2:    in  std_Logic;
  clr_2:    in  std_Logic);

  );

end entity stack;


architecture logic of stack is

----------------------------------------------------------------------------------

  component unidade_74LS194 is

  port(
        d:  in  std_Logic_Vector ( 3 DOWNTO 0 );
        q:  out std_Logic_Vector ( 3 DOWNTO 0 );
        s:  in  std_Logic_Vector ( 1 DOWNTO 0 );
        L:  in  std_Logic;
        R:  in  std_Logic;
        clk:    in  std_Logic;
        clr:    in  std_Logic);

  end component;

----------------------------------------------------------------------------------

Q_3, vector_d_3: STD_LOGIC_VECTOR(3 downto 0);
Q_2, vector_d_2: STD_LOGIC_VECTOR(3 downto 0);
Q_1, vector_d_1: STD_LOGIC_VECTOR(3 downto 0);
Q_0, vector_d_0: STD_LOGIC_VECTOR(3 downto 0);


begin

vector_d_3(3) <= A(3);
vector_d_3(2) <= Q_3(2);
vector_d_3(1) <= Q_3(1);
vector_d_3(0) <= Q_3(0);

R3: unidade_74LS194 port map(vector_d_3, Q_3, S_aux, Q_1(3), A(3), clk_2, clr_2);

Q_aux(3) <= Q_3(3);


vector_d_2(3) <= A(2);
vector_d_2(2) <= Q_2(2);
vector_d_2(1) <= Q_2(1);
vector_d_2(0) <= Q_2(0);

R2: unidade_74LS194 port map(vector_d_2, Q_2, S_aux, Q_2(3), A(2), clk_2, clr_2);

Q_aux(2) <= Q_2(3);


vector_d_1(3) <= A(1);
vector_d_1(2) <= Q_1(2);
vector_d_1(1) <= Q_1(1);
vector_d_1(0) <= Q_1(0);

R1: unidade_74LS194 port map(vector_d_1, Q_1, S_aux, Q_1(3), A(1), clk_2, clr_2);

Q_aux(1) <= Q_1(3);

vector_d_0(3) <= A(0);
vector_d_0(2) <= Q_0(2);
vector_d_0(1) <= Q_0(1);
vector_d_0(0) <= Q_0(0);

R1: unidade_74LS194 port map(vector_d_0, Q_0, S_aux, Q_0(3), A(0), clk_2, clr_2);

Q_aux(0) <= Q_0(3);



end logic;

74LS194部分：

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity unidade_74LS194 is
    port(
          d:    in  std_Logic_Vector ( 3 DOWNTO 0 );
          q:    out std_Logic_Vector ( 3 DOWNTO 0 );
          s:    in  std_Logic_Vector ( 1 DOWNTO 0 );
          L:    in  std_Logic;
          R:    in  std_Logic;
          clk:  in  std_Logic;
          clr:  in  std_Logic);
end entity unidade_74LS194;

architecture logic of unidade_74LS194 is

  SIGNAL flw: std_Logic_Vector ( 3 DOWNTO 0 );

  procedure logic_pattern (
    signal ff0: in std_Logic;
    signal ff1: in std_Logic;
    signal ff2: in std_Logic;
    signal b: in std_Logic;
    signal s: in std_Logic_Vector ( 1 DOWNTO 0 );
    signal o: out std_Logic
        ) is
  begin
    o <= (
        ( b and (not s(0)) and (not s(1)) ) OR
        ( ff0 and (not s(0)) and s(1) ) OR
        ( ff1 and s(0) and (not s(1)) ) OR
        ( ff2 and s(0) and s(1) )
    );

  end procedure;

begin

  main: PROCESS ( d, s, R, L, clr, clk, flw )
  begin

    flw <= "0000";

     If ( clr = '0' ) then
       flw <= "0000";

     elsif ( clk = '0' and clk'event ) then

       logic_pattern ( R, flw(1), flw(0), d(0), s, flw(0) );
       logic_pattern ( flw(0), flw(2), flw(1), d(1), s, flw(1) );
       logic_pattern ( flw(1), flw(3), flw(2), d(2), s, flw(2) );
       logic_pattern ( flw(2), L, flw(3), d(3), s, flw(3) );
  end if;

  end process; -- main
  q <= flw;

end architecture logic;

真正让我恼火的是74LS194逻辑。它是负责推送/弹出操作的部分。

Answer 1

我不知道VHDL (更像是verilog的人)，但堆栈基本上只是一个内存，一个递增和递减的地址，以及用于写入/读取数据的输入和输出总线。

当你说你有一个‘4位1’时，我想你的意思是内存条目是4位宽的，所以要使‘8位1’，只需将内存宽度从4增加到8，并改变输入和输出。