如何使用blackbox生成代码到RTL？

Question

当我想转换代码凿到verilog与黑盒，我有错误。我怎么才能修复它？

[error] /data/workspace/chisel/chisel3-3.1.8/src/main/scala/tap/dti_bypass_register.scala:45:18: overloaded method value execute with alternatives:

import chisel3._
import chisel3.util._
  class dti_bypass_register extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle {
    val clk_DR          = Input (Clock())// Bypass register clock
    val TDI             = Input (UInt(1.W))// data in
    val bypass_en       = Input (Bool())// enable signal
    val captureDR       = Input (Bool())// captureDR signal

    val TDO_bypass      = Output (UInt(1.W))// Serial data out
  })
    setResource("/dti_bypass_register.v")

}

object dti_bypass_registerDriver extends App {
  chisel3.Driver.execute(args, () => new dti_bypass_register)
}

Answer 1

Chisel不接受BlackBoxes作为顶层模块。由于BlackBoxes仅仅是我们为其发出Verilog实例化的接口，因此Chisel对它们并没有什么真正的用处。