电路无法递增

Question

我正在尝试创建一个3位4位二进制编码的递增电路。该电路的目的是在每个上升时钟沿之后递增BCD，但是，它会递增，但在时钟沿之后又会返回零。我希望代码从count1开始递增，一旦count1达到9，count2递增，然后count3也是如此。我不能附加模拟，但我可以给你测试代码，以节省你的时间，如果你愿意帮助，谢谢。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;


entity bit12_BCD_incrementor is
    Port ( 
       clk  :  in STD_LOGIC ;
       reset:  in STD_LOGIC ;
       inc  :  in STD_LOGIC ;
       out1 :  out STD_LOGIC_VECTOR (3 downto 0);
       out2 :  out STD_LOGIC_VECTOR (3 downto 0);
       out3 :  out  STD_LOGIC_VECTOR (3 downto 0)
       );
end bit12_BCD_incrementor;

architecture BCD_arch of bit12_BCD_incrementor is

signal count1 , c1next : unsigned(3 downto 0) ;
signal count2 , c2next : unsigned(3 downto 0) ;
signal count3 , c3next : unsigned(3 downto 0) ;
signal fb ,fzero, zero : std_logic;

begin
out1 <= std_logic_vector (count1);
out2 <= std_logic_vector (count2);
out3 <= std_logic_vector (count3);

process(clk, reset, inc)
begin

count1 <= ( others => '0');
count2 <= ( others => '0');
count3 <= ( others => '0');



if (reset = '1') then
   count1 <= ( others => '0')  ;
   count2 <= ( others => '0') ;
   count3 <= ( others => '0') ;


elsif (rising_edge(clk)) then 
  if (inc = '1') then
   count1 <= count1 + 1;

elsif (count1 = 9)    then
 if (inc = '1') then
  count1 <= ( others => '0' ) ;
  count2 <= count2 + 1 ;


elsif (count1 = 9)then 
 if (count2 = 9) then
 count3 <= count3 + 1;






end if;
end if;
end if;
end if;



end process;

Answer 1

你的process错了。你不会在达到你的极限后将计数器重置为零，而且你在代码中的两个不同的地方写你的计数器！

process(clk, reset, inc)
begin

count1 <= ( others => '0');
...

和

elsif(rising_edge(clk)) then 
   if(inc = '1') then
      count1 <= count1 + 1;

因此，在流程的每个周期中，您的count变量都设置为0。清理您的process的if语句，为您的计数器添加重置条件，您的解决方案就可以工作了：

entity DigitCounter is
    Port ( Clk          : in STD_LOGIC;
           Reset        : in STD_LOGIC;
           Direction    : in STD_LOGIC;
           Out1         : out STD_LOGIC_VECTOR(3 downto 0);
           Out2         : out STD_LOGIC_VECTOR(3 downto 0);
           Out3         : out STD_LOGIC_VECTOR(3 downto 0)
           );
end DigitCounter;

architecture DigitCounter_Arch of DigitCounter is

    signal Counter1         : INTEGER := 0;
    signal Counter2         : INTEGER := 0;
    signal Counter3         : INTEGER := 0;

    signal CountDirection   : INTEGER := 0;
    signal Limit            : INTEGER := 0;
    signal ResetValue       : INTEGER := 0;

begin

    CountDirection <= 1 when (Direction = '1') else -1;
    Limit <= 9 when (Direction = '1') else 0;
    ResetValue <= 0 when (Direction = '1') else 9;

    process(Clk, Reset, ResetValue)
    begin
        if(Reset = '1') then
           Counter1 <= ResetValue;
           Counter2 <= ResetValue;
           Counter3 <= ResetValue;
        elsif(rising_edge(Clk)) then
            Counter1 <= Counter1 + CountDirection;

            if(Counter1 = Limit) then
                Counter1 <= ResetValue;
                Counter2 <= Counter2 + CountDirection;

                if(Counter2 = Limit) then
                    Counter2 <= ResetValue;
                    Counter3 <= Counter3 + CountDirection;

                    if(Counter3 = Limit) then
                        Counter3 <= ResetValue;
                    end if;
                end if;
            end if;
        end if;
    end process;

    Out1 <= std_logic_vector(to_unsigned(Counter1, Out1'length));
    Out2 <= std_logic_vector(to_unsigned(Counter2, Out2'length));
    Out3 <= std_logic_vector(to_unsigned(Counter3, Out3'length));

end DigitCounter_Arch;

使用下面的测试平台

entity Top_TB is
--  Port ( );
end Top_TB;

architecture Behavioral of Top_TB is

    constant ClockPeriod : TIME := 200 ns;

    signal Clock : STD_LOGIC := '0';
    signal Reset : STD_LOGIC := '1';

    signal Out1 : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
    signal Out2 : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
    signal Out3 : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');

    component Top is
        Port ( Clk : in STD_LOGIC;
               Reset : in STD_LOGIC;
               Inc : in STD_LOGIC;
               Out1 : out STD_LOGIC_VECTOR(3 downto 0);
               Out2 : out STD_LOGIC_VECTOR(3 downto 0);
               Out3 : out STD_LOGIC_VECTOR(3 downto 0));
    end component;

begin

    -- Clock generation
    process begin
        wait for (ClockPeriod / 2);
        Clock <= '1';
        wait for (ClockPeriod / 2);
        Clock <= '0';
    end process;

    UUT : component Top port map (  Clk => Clock,
                                    Reset => Reset,
                                    Inc => '1',
                                    Out1 => Out1,
                                    Out2 => Out2,
                                    Out3 => Out3
                                    );

    -- Stimulus
    process begin
        wait for 10 ns;
        Reset <= '0';
    end process;

end Behavioral;

您将获得以下输出

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