Chisel PeekPokeTester中的Printf与相同RTL上的verilator不同

Question

在Chisel的iotester中打印似乎输出了寄存器值的更新版本，这使得相同的Chisel打印代码在Chisel后端和verilator后端的行为不同。

当使用Chisel后端时，打印似乎只是记录硬件对象的引用，但是在对当前步骤进行逻辑模拟之后执行打印，然后引用返回一个更新的值。

我已经搜索过Chisel的问题和凿子用户组，但是很少有关于这个话题的讨论。

下面是一个自包含的代码示例op顶部的凿模板回购。

package myrtl

import chisel3._
import chisel3.iotesters._

class Foo extends Module {

  val io = IO(new Bundle {
    val in = Input(UInt(32.W))
    val out = Output(UInt(32.W))
  })

  val v = Wire(UInt(32.W))
  when (v === 0.U) {
    printf(p"v $v\n")
  }

  val reg = RegInit(0.U(32.W))
  reg := io.in
  io.out := reg
  v := reg
}

class FooTester(dut: Foo) extends PeekPokeTester(dut) {
  poke(dut.io.in, 32)
  step(1)
}

object TestMain extends App {
  iotesters.Driver.execute(args, () => new Foo)(dut => new FooTester(dut))
}

注意printf的条件。可笑的是，v === 0.U启用了打印，但将此v输出为32的值。

Answer 1

我认为这是一个报告的错误，其中printf语句没有正确计算它们的依赖项(并且是固定的)。

• treadle#70

在过去一年中，有一些因素可能是修复这一问题的原因：

• treadle#81
• treadle#84
• treadle#113

您能否尝试在sonatype上切换到1.3-SNAPSHOT并重新测试？

diff --git a/build.sbt b/build.sbt
index 6d18fe7..c13d44d 100644
--- a/build.sbt
+++ b/build.sbt
@@ -41,11 +41,10 @@ resolvers ++= Seq(

 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
 val defaultVersions = Map(
-  "chisel3" -> "3.1.+",
-  "chisel-iotesters" -> "[1.2.5,1.3.0["
+  "chisel-iotesters" -> "1.3-SNAPSHOT"
   )

-libraryDependencies ++= Seq("chisel3","chisel-iotesters").map {
+libraryDependencies ++= Seq("chisel-iotesters").map {
   dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }

 scalacOptions ++= scalacOptionsVersion(scalaVersion.value)

通过对build.sbt的这些修改，我能够看到不打印的预期行为。这与Verilator不同，Verilator在模拟开始之前有一个打印。使用1.3-SNAPSHOT

sbt:chisel-module-template> test:runMain myrtl.TestMain --backend-name treadle
[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list
[info] Running myrtl.TestMain --backend-name treadle
[info] [0.001] Elaborating design...
[info] [0.108] Done elaborating.
Total FIRRTL Compile Time: 408.8 ms
file loaded in 0.071117471 seconds, 15 symbols, 12 statements
[info] [0.001] SEED 1568033935603
test Foo Success: 0 tests passed in 6 cycles in 0.012474 seconds 481.00 Hz
[info] [0.003] RAN 1 CYCLES PASSED
[success] Total time: 2 s, completed Sep 9, 2019 8:58:56 AM

在使用verilator时(输出的一些片段)：

sbt:chisel-module-template> test:runMain myrtl.TestMain --backend-name verilator
[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list
[info] Running myrtl.TestMain --backend-name verilator
[info] [0.001] Elaborating design...
[info] [0.108] Done elaborating.
Total FIRRTL Compile Time: 440.6 ms
[info] [0.001] SEED 1568034082729
[info] [0.007] v          0
[info] [0.007]          0
Enabling waves..
Exit Code: 0
[info] [0.011] RAN 1 CYCLES PASSED
[success] Total time: 4 s, completed Sep 9, 2019 9:01:25 AM