奇异RTL输出

Question

优胜0.8

我的一位同事向Yosys扔了一些随机 verilog代码，看看它是如何反应的。

下面是：

module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2);


reg ctr = 0;
reg[24:0] counter = 2;
always@(posedge clk) begin
    if (ctr == 1) begin
        ctr <= 0;
        counter <= counter + 1;
    end
    else
        ctr <= 1;
end

assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule

而Yosys则使用命令yosys -o synth.v x.v抛出：

module top(clk, led, led2, to_port1, to_port2);

  reg [24:0] _0_;
  reg _1_;
  reg [24:0] _2_;
  reg _3_;
  wire [31:0] _4_;
  wire _5_;
  input clk;
  reg [24:0] counter;
  reg ctr;
  input led;
  output led2;
  output to_port1;
  output [24:0] to_port2;

  assign _4_ = counter + 32'd1;
  assign _5_ = ctr == 32'd1;
  always @* begin
    _3_ = 1'h0;
  end
  always @* begin
  end
  always @({  }) begin
      ctr <= _3_;
  end
  always @* begin
    _2_ = 25'h0000002;
  end
  always @* begin
  end
  always @({  }) begin
      counter <= _2_;
  end
  always @* begin
    _1_ = ctr;
    _0_ = counter;
    casez (_5_)
      1'h1:
        begin
          _1_ = 1'h0;
          _0_ = _4_[24:0];
        end
      default:
          _1_ = 1'h1;
    endcase
  end
  always @(posedge clk) begin
      ctr <= _1_;
      counter <= _0_;
  end
  assign led2 = ctr;
  assign to_port1 = led;
  assign to_port2 = counter;
endmodule

有些构造最终会变得复杂。上述结果代码不能由最近的verilog编译器编译，而原始编译器可以编译。

为什么是always @({ }) begin构造和空always @* begin？我们错过了什么选择吗？

谢谢

Answer 1

通常，由于Yosys对读- In Verilog的内部表示的性质，您应该始终在读写Verilog之间运行proc (-p proc)。