测试DSPComplex ROM

Question

我正在努力构建一个DSPComplex ROM仍然，并已经击中了我认为可能是一个实际的Chisel问题。

我已经构建了ROM，可以从看似合理的代码中生成verilog输出，但似乎无法用最基本的测试人员来测试模块。下面我把它简化为最基本的检查。

此错误是堆栈溢出，如下所示：

$ sbt 'testOnly taylor.TaylorTest'
Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=8G; support was removed in 8.0
[info] Loading settings from plugins.sbt ...
[info] Loading project definition from /home/jcondley/Zendar/kodo/ZenFPGA/chisel/project
[info] Loading settings from build.sbt ...
[info] Set current project to zen-chisel (in build file:/home/jcondley/Zendar/kodo/ZenFPGA/chisel/)
[info] Compiling 1 Scala source to /home/jcondley/Zendar/kodo/ZenFPGA/chisel/target/scala-2.12/classes ...
[warn] there were 5 feature warnings; re-run with -feature for details
[warn] one warning found
[info] Done compiling.
[info] Compiling 1 Scala source to /home/jcondley/Zendar/kodo/ZenFPGA/chisel/target/scala-2.12/test-classes ...
[warn] there were two deprecation warnings (since chisel3, will be removed by end of 2017); re-run with -deprecation for details
[warn] there were two feature warnings; re-run with -feature for details
[warn] two warnings found
[info] Done compiling.
[info] [0.004] Elaborating design...
[deprecated] DspComplex.scala:22 (1029 calls): isLit is deprecated: "isLit is deprecated, use litOption.isDefined"
[deprecated] DspComplex.scala:22 (1029 calls): litArg is deprecated: "litArg is deprecated, use litOption or litTo*Option"
[deprecated] DspComplex.scala:23 (1029 calls): isLit is deprecated: "isLit is deprecated, use litOption.isDefined"
[deprecated] DspComplex.scala:23 (1029 calls): litArg is deprecated: "litArg is deprecated, use litOption or litTo*Option"
[warn] There were 4 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn]   In the sbt interactive console, enter:
[warn]     set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn]   or, in your build.sbt, add the line:
[warn]     scalacOptions := Seq("-unchecked", "-deprecation")
[info] [1.487] Done elaborating.
Total FIRRTL Compile Time: 1887.8 ms
Total FIRRTL Compile Time: 770.6 ms
End of dependency graph
Circuit state created
[info] TaylorTest:
[info] TaylorWindow
[info] taylor.TaylorTest *** ABORTED ***
[info]   java.lang.StackOverflowError:
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.evaluate(LoFirrtlExpressionEvaluator.scala:264)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.$anonfun$resolveDependency$1(LoFirrtlExpressionEvaluator.scala:453)
[info]   at firrtl_interpreter.Timer.apply(Timer.scala:40)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.resolveDependency(LoFirrtlExpressionEvaluator.scala:445)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.getValue(LoFirrtlExpressionEvaluator.scala:81)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.evaluate(LoFirrtlExpressionEvaluator.scala:304)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.$anonfun$resolveDependency$1(LoFirrtlExpressionEvaluator.scala:453)
[info]   at firrtl_interpreter.Timer.apply(Timer.scala:40)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.resolveDependency(LoFirrtlExpressionEvaluator.scala:445)
[info]   at firrtl_interpreter.LoFirrtlExpressionEvaluator.getValue(LoFirrtlExpressionEvaluator.scala:81)
[info]   ...

从这里看，这有点像另一个ROM问题：

https://github.com/freechipsproject/chisel3/issues/642

但在这里尝试一下奇克的回答：

export SBT_OPTS="-Xmx2G -XX:+UseConcMarkSweepGC -XX:+CMSClassUnloadingEnabled -XX:MaxPermSize=2G -Xss2M  -Duser.timezone=GMT"

似乎没有解决这个问题(其中一个选项，MaxPermSize被忽略了)

这是一个合法的带有ROM的Chisel错误，还是这里正在发生的其他事情？

具有ROM的实际模块：

package taylor

import chisel3._
import chisel3.util._
import chisel3.experimental.FixedPoint
import dsptools.numbers._
import scala.io.Source


class TaylorWindow(len: Int, window: Seq[FixedPoint]) extends Module {
    val io = IO(new Bundle {
        val d_valid_in = Input(Bool())
        val sample = Input(DspComplex(FixedPoint(16.W, 8.BP), FixedPoint(16.W, 8.BP)))
        val windowed_sample = Output(DspComplex(FixedPoint(32.W, 8.BP), FixedPoint(32.W, 8.BP)))
        val d_valid_out = Output(Bool())
    })
     val win_coeff = VecInit(window.map(x=>DspComplex.wire(x, FixedPoint(0, 16.W, 8.BP))).toSeq) // ROM storing our coefficients.       

    io.d_valid_out := io.d_valid_in
    val counter = RegInit(UInt(10.W), 0.U)

    // Implicit reset
    io.windowed_sample:= io.sample * win_coeff(counter)
    when(io.d_valid_in) {
        counter := counter + 1.U
    }
}

object TaylorDriver extends App {                                                                                                       
    val filename = "src/test/test_data/taylor_coeffs"                                                                                   
    val coeff_file = Source.fromFile(filename).getLines                                                                                 
    val double_coeffs = coeff_file.map(x => x.toDouble)                                                                                 
    val fp_coeffs = double_coeffs.map(x => FixedPoint.fromDouble(x, 16.W, 8.BP))                                                        
    val fp_seq = fp_coeffs.toSeq                                                                                                        
    chisel3.Driver.execute(args, () => new TaylorWindow(1024, fp_seq))                                                                  
} 

测试人员代码：

package taylor

import chisel3._
import chisel3.util._
import chisel3.experimental.FixedPoint
import dsptools.numbers.implicits._
import scala.io.Source


import chisel3.iotesters
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}

class TaylorWindowUnitTest(dut: TaylorWindow) extends PeekPokeTester(dut) {

    val filename = "src/test/test_data/taylor_coeffs"
    val coeff_file = Source.fromFile(filename).getLines
    val double_coeffs = coeff_file.map(x => x.toDouble)
    val fp_coeffs = double_coeffs.map(x => FixedPoint.fromDouble(x, 16.W, 8.BP))
    val fp_seq = fp_coeffs.toSeq

  poke(dut.io.d_valid_in, Bool(false))
  expect(dut.io.d_valid_out, Bool(false))
}

class TaylorTest extends ChiselFlatSpec {
    behavior of "TaylorWindow"

    backends foreach {backend =>
        it should s"test the basic Taylow Window" in {
            Driver(() => new TaylorWindow(1024, getSeq()), backend)(c => new TaylorWindowUnitTest(c)) should be (true)
        }
    }

  def getSeq() : Seq[FixedPoint] = {
    val filename = "src/test/test_data/taylor_coeffs"
    val coeff_file = Source.fromFile(filename).getLines
    val double_coeffs = coeff_file.map(x => x.toDouble)
    val fp_coeffs = double_coeffs.map(x => FixedPoint.fromDouble(x, 16.W, 8.BP))
    fp_coeffs.toSeq
    }
}

Answer 1

这看起来像是firrtl解释器(基于Scala的Chisel模拟器之一)中的一个失败，它可能会出现许多大型firrtl结构的问题。如果安装了verilator，可以尝试更改吗？

backends foreach {backend =>

至

Seq("verilator") foreach {backend =>

看看会发生什么。另一个值得尝试的想法是Treadle，它是解释器的新版本，尚未完全发布，但可在ecosystem生态系统的快照版本中使用。它也应该能处理好这件事。