比较分配给std_logic_vector的整数值

Question

我有一个0到23的整数数组，它存储范围0到2的值，类似于ex：

type t_slave_24symbol is array (0 to 23) of integer range 0 to 2;
signal slave_24symbol   : t_slave_24symbol;

type nibble_array is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0); 
signal nibble : nibble_array;

signal nibble_full : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";

现在，我想将这个字符串分割成3的序列，并进行如下比较

nibble(0) <= "0000" when slave_24symbol(012) = 120 else-- 
        "0001" when slave_24symbol(012)= 200 else
        "0010" when slave_24symbol(012)= 020 else
        "1111";

但后来

nibble(3) <= "0000" when slave_24symbol(91011) = 012 else

。。。

在最后

nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4) 
& nibble(5) & nibble(6) & nibble(7);

我该怎么做？因为我想分配char 9，10和11等等。

Answer 1

这个问题显示了python语法思想。

在std_logic_vector数组中，有一个约束整数数组被转换为二进制表示。

首先是一个工作的Minimal, Complete, and Verifiable example，用于分配一个nibble元素：

library ieee;
use ieee.std_logic_1164.all;

entity depython is
end entity;

architecture foo of depython is 
    type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
    signal slave_24symbol: t_slave_24symbol (0 to 23);

    type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0); 
    signal nibble:      nibble_array;
    signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
    subtype nyyblet is t_slave_24symbol (0 to 2);
begin

    -- nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
    --         "0001" when slave_24symbol(012)= 200 else
    --         "0010" when slave_24symbol(012)= 020 else
    --         "1111";

    -- BECOMES:

    nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1, 2, 0) else
                 "0001" when slave_24symbol(0 to 2) = nyyblet'(2, 0, 0) else
                 "0010" when slave_24symbol(0 to 2) = nyyblet'(0, 2, 0) else
                 "1111";
end architecture; 

类型t_slave_24symbol已更改为无约束数组定义，并声明信号slave_24symbol提供该子类型。(这在2008年被称为无界数组定义)。

将slave_24symbol切片的索引范围改为VHDL语法。在每个条件中计算的表达式的值范围已经更改为VHDL语法，它使用一个聚合，其类型由需要子类型定义的限定表达式提供。子类型声明需要无约束/无界数组定义。

指定子类型需要限定表达式，因为数组类型的预定义相等运算符在无约束操作数上操作--您可以测试两个不同长度数组的相等性，它们总是不相等的。(在处理空数组时很方便)。

注意，字符串文本的类型(例如"0010")是由上下文决定的，元素值('0'，'1')必须与数组类型(此处为std_ulogic)的元素类型(此处为std_logic_vector)兼容。

这将分析、阐述和模拟(对slave_24symbol的每个元素使用默认值(0、0、0)，每个进程将在初始化期间执行一次，并发赋值语句将被详细阐述为包含在进程语句中的等效顺序赋值语句)。

现在我们讨论如何在一个新的体系结构中转换nibble的所有元素：

architecture sequential of depython is
    type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
    signal slave_24symbol: t_slave_24symbol (0 to 23);

    type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0); 
    signal nibble:      nibble_array;
    signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
    subtype nyyblet is t_slave_24symbol (0 to 2);

    function nybble (nyb: nyyblet) return std_logic_vector is
       --  retv:   std_logic_vector(3 downto 0);
    begin
        if    nyb = nyyblet'(1, 2, 0) then
            return "0000";
        elsif nyb = nyyblet'(2, 0, 0) then
            return "0001";
        elsif nyb = nyyblet'(0, 2, 0) then 
            return "0010";
        else 
            return "1111";
        end if;
    end function;
begin    

    -- nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1,2,0) else
    --              "0001" when slave_24symbol(0 to 2) = nyyblet'(2,0,0) else
    --              "0010" when slave_24symbol(0 to 2) = nyyblet'(0,2,0) else
    --              "1111";

-- but later
--
-- nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
--
-- . . .
--
-- and at the end
--
-- nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
-- & nibble(5) & nibble(6) & nibble(7);

    process (slave_24symbol)
    begin
        for i in nibble'range loop
            nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
        end loop;
    end process;

end architecture;

在这里，函数调用用于隐藏一些复杂性。循环语句中的顺序赋值语句(序列语句本身)使用偏移算法来处理被求值的slave_24symbol的三个约束整数的所有八个片。

由于问题显示在条件信号分配(这里是并发信号分配)中分配了一个nibble元素，因此使用generate语句的并发赋值版本：

architecture concurrent of depython is
    type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
    signal slave_24symbol: t_slave_24symbol (0 to 23);

    type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0); 
    signal nibble:      nibble_array;
    signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
    subtype nyyblet is t_slave_24symbol (0 to 2);

    function nybble (nyb: nyyblet) return std_logic_vector is
       --  retv:   std_logic_vector(3 downto 0);
    begin
        if    nyb = nyyblet'(1, 2, 0) then
            return "0000";
        elsif nyb = nyyblet'(2, 0, 0) then
            return "0001";
        elsif nyb = nyyblet'(0, 2, 0) then 
            return "0010";
        else 
            return "1111";
        end if;
    end function;
begin    

    -- process (slave_24symbol)
    -- begin
    --     for i in nibble'range loop
    --         nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
    --     end loop;
    -- end process;
NIBBLE_IT:
    for i in nibble'range generate
        nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
    end generate;

end architecture;

所有显示的体系结构都对所有索引和切片进行分析、详细阐述和模拟演示，这些索引和切片都属于子类型界限。

注意，还可以将循环语句注入参数类型为t_slave_24symbol的函数，并同时或顺序执行一次赋值。这还允许检测不由3个整数的倍数组成的参数值(因为t_slave_24symbol类型被声明为无约束/无界)。通过声明一个新类型并使t_slave_24symbol和nyyblet子类型成为新类型，可以避免任何参数值检测：

architecture all_in_one_function of depython is
    type c_integer_array is array (natural range <>) of integer range 0 to 2;
    subtype t_slave_24symbol is c_integer_array (0 to 23);
    signal slave_24symbol: t_slave_24symbol := (
                    1,2,0, 2,0,0, 0,2,0, 0,0,0, 0,0,1, 0,0,2, 0,1,0, 0,1,1);
    signal nibble_full:    std_logic_vector (31 downto 0);

    function nybble (slave: t_slave_24symbol) return std_logic_vector is
        type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0); 
        variable nib:      nibble_array;
        subtype nyyblet is c_integer_array (0 to 2);
    begin
        for i in nib'range loop
            if    slave(3 * i to 2 + i * 3) = nyyblet'(1, 2, 0) then
                nib(i) := "0000";
            elsif slave(3 * i to 2 + i * 3) = nyyblet'(2, 0, 0) then
                nib(i) := "0001";
            elsif slave(3 * i to 2 + i * 3) = nyyblet'(0, 2, 0) then 
                nib(i) := "0010";
            else 
                nib(i) := "1111";
            end if;
        end loop;
        return nib(0) & nib(1) & nib(2) & nib(3) & 
               nib(4) & nib(5) & nib(5) & nib(7);
    end function;

    function to_string (inp: std_logic_vector) return string is
        variable image_str: string (1 to inp'length);
        alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
        end loop;
        return image_str;
    end function;
begin    
NIBBLE_IT:
    nibble_full <= nybble(slave_24symbol);
    process
    begin
        wait for 0 ns;
        report "nibble_full = " & to_string (nibble_full);
        wait;
    end process;
end architecture;

to_string函数是为了与2008年之前的版本兼容而添加的。初始化信号_slave_24symbol以证明转换是成功的：

/usr/local/bin/ghdl -a epython1.vhdl /usr/local/bin/ghdl -e depython /usr/local/bin/ghdl -r depython 深度1.vhdl:79:9：@0MS：(报告注)：nibble_full =000000010010111111111111111111111111