我编写了以下代码:verilog代码只是大门:
import Chisel._
class BB_tb extends Bundle {
val a = Bits(INPUT, 1)
val b = Bits(INPUT, 1)
val c = Bits(OUTPUT, 1)
}
class BlackBox_tb extends BlackBox {
val io = new BB_tb()
}但是当我试图运行它时,我会发现这些错误:我不知道它意味着什么
运行BlackBox_tb --后端c-targetDir../BlackBox_tb--编译信息-将一个Scala源代码编译为BlackBox_tb在TutorialProblems.TutorialProblems$.main(problems.scala:9) at TutorialProblems.TutorialProblems.main(problems.scala) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native方法上运行TutorialProblems.TutorialProblems BlackBox_tb --后端c --targetDir ./仿真器--编译error scala.MatchError: BlackBox_tb (类java.lang.String) scala.MatchError: BlackBox_tb (类java.lang.String)sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) at java.lang.reflect.Method.invoke(Method.java:498)跟踪堆栈跟踪抑制:运行最后一次编译:为完整输出运行。java.lang.RuntimeException:非零退出代码:1在scala.sys.package$.error(package.scala:27)跟踪堆栈跟踪抑制:运行最后的编译:运行为完整的输出。error非零退出代码:1错误总时间: 18秒,2017年9月9日下午2:30:45完成
发布于 2017-09-11 16:53:27
在Chisel2中这样做有多重要?Chisel3现在是标准版本,其中很多东西都更容易得到更好的支持。在chisel3中,以下内容适用于我。
// See LICENSE for license details.
package essan
import chisel3._
import chisel3.iotesters.PeekPokeTester
import chisel3.util.HasBlackBoxResource
class BBAnd extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val a = Input(Bool())
val b= Input(Bool())
val result = Output(Bool())
})
val blackBoxFloatVerilog = "/essan/BBAnd.v"
setResource(blackBoxFloatVerilog)
}
class BBWrapper extends Module {
val io = IO(new Bundle {
val a = Input(Bool())
val b= Input(Bool())
val result = Output(Bool())
})
val tb = Module(new BBAnd)
tb.io.a := io.a
tb.io.b := io.b
io.result := tb.io.result
}
class BlackBox_tbTests(c: BBWrapper) extends PeekPokeTester(c) {
// FILL THIS IN HERE
poke(c.io.a, 1)
poke(c.io.b, 1)
// FILL THIS IN HERE
step(1)
expect(c.io.result, 1)
}
object BlackBox_tbTests {
def main(args: Array[String]): Unit = {
iotesters.Driver(() => new BBWrapper, "verilator") { c =>
new BlackBox_tbTests(c)
}
}
}我使用以下方法作为基础verilog实现
module BBAnd(
input [63:0] a,
input [63:0] b,
output reg [63:0] result
);
always @* begin
result = a & b;
end
endmodule唯一真正的诀窍是找出把verilog实现放在哪里。文件树看起来像。
src
src/main
src/main/resources
src/main/resources/essan
src/main/resources/essan/BBAnd.v
src/main/scala
src/main/scala/essan
src/main/scala/essan/BlackBoxAnd.scala我从命令行运行测试
sbt 'runMain essan.BlackBox_tbTests'https://stackoverflow.com/questions/46131235
复制相似问题