Fifo块实现

Question

我在系统verilog中写了一个先进先出，我试着把一些数据推到这个先进先出(我写了一个tb)，当我推入数据时，fifo_wr_ptr，fifo_fre_space，fifo_used_space不会更新(只有数据写到内存)

我会很高兴得到帮助(例如，为什么我的ptr不会递增1)

非常感谢！这是我的模拟，它显示了我的问题：

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我附上了我的代码：

module fifo
#(parameter WIDTH = 32,   parameter DEPTH = 64 ) (   clk,   rst_l,   sw_rst,   fifo_din,   fifo_push_en,   fifo_pop_en,   fifo_dout,   fifo_o_full,   fifo_o_empty,   fifo_used_space,   fifo_free_space );




   function integer log2; //can use the $clog2() function
      input [31:0] value;
      reg [31:0]   value_tmp;
      begin      value_tmp = value;      for(log2=0; value_tmp>0; log2=log2+1)
       value_tmp=(value_tmp>>1);
      end    endfunction

localparam DEPTH_LOG2 = log2(DEPTH);

//interface  input clk; input rst_l; input sw_rst; input[WIDTH-1:0] fifo_din; input fifo_push_en; input fifo_pop_en; output logic[WIDTH-1:0] fifo_dout; output logic fifo_o_full; output logic fifo_o_empty; output logic[DEPTH_LOG2-1:0] fifo_used_space; output logic[DEPTH_LOG2-1:0] fifo_free_space; logic debug_flag; //internal logic logic[WIDTH-1:0] mem[DEPTH_LOG2-1:0]; logic[DEPTH_LOG2-1:0] fifo_rd_ptr,fifo_wr_ptr;

assign fifo_o_empty = (fifo_used_space==0); assign fifo_o_full  = (fifo_free_space==0);


always @ (posedge clk or negedge rst_l) begin    if(~rst_l) begin 
     fifo_free_space <= DEPTH;
     fifo_used_space <= 0;
     fifo_rd_ptr <= 0;
     fifo_wr_ptr <= 0;
     debug_flag <=0 ;

  end else if (~sw_rst) begin
     fifo_free_space <= DEPTH;
     fifo_used_space <= 0;
     fifo_rd_ptr <= 0;
     fifo_wr_ptr <= 0;
     debug_flag <= 0;

 end else if(fifo_push_en==1 && fifo_o_full==0 && fifo_pop_en==0) begin //the fifo isn't full and can perform the write trasaction (and no read transaction)
     fifo_used_space <= fifo_used_space + 1;
     fifo_free_space <= fifo_free_space - 1;
     mem[fifo_wr_ptr]<= fifo_din;
     debug_flag <= 1;
     if(fifo_wr_ptr == (DEPTH - 1)) 
        fifo_wr_ptr <= 0;
     else
        fifo_wr_ptr++;


     end else if (fifo_pop_en==1 && fifo_o_empty==0 && fifo_push_en==0) begin // the fifo isn't empty and can perform the read trasaction (and no write trasaction)
     fifo_used_space <= fifo_used_space - 1;
     fifo_free_space <= fifo_free_space + 1;
     fifo_dout       <= mem[fifo_rd_ptr];
     if(fifo_rd_ptr == (DEPTH - 1)) begin 
        fifo_rd_ptr  <= 0;
     end else begin 
        fifo_rd_ptr  <= fifo_rd_ptr + 1;
     end  end else begin

     fifo_rd_ptr     <= fifo_rd_ptr;
     //fifo_wr_ptr     <= fifo_wr_ptr;
     //fifo_dout       <= fifo_dout;
     //fifo_used_space <= fifo_used_space;
     fifo_free_space <= fifo_free_space;   end end

endmodule

下面是tb代码：

`define WIDTH 32
`define DEPTH 64

module fifo_tb();


   function integer log2; //can use the $clog2() function
      input [31:0] value;
      reg [31:0]   value_tmp;
      begin
     value_tmp = value;
     for(log2=0; value_tmp>0; log2=log2+1)
       value_tmp=(value_tmp>>1);
      end
   endfunction


localparam DEPTH_LOG2 = log2(`DEPTH);


logic clk,rst_l,sw_rst,fifo_push_en,fifo_pop_en,fifo_o_full,fifo_o_empty;
logic[`WIDTH-1:0] fifo_din,fifo_dout,tempdata;
logic[DEPTH_LOG2-1:0] fifo_used_space,fifo_free_space;

fifo #(`WIDTH,`DEPTH) ff(.clk(clk), .rst_l(rst_l), .sw_rst(sw_rst), .fifo_din(fifo_din),
            .fifo_push_en(fifo_push_en), .fifo_pop_en(fifo_pop_en),
            .fifo_dout(fifo_dout), .fifo_o_full(fifo_o_full), .fifo_o_empty(fifo_o_empty),
            .fifo_used_space(fifo_used_space), .fifo_free_space(fifo_free_space) );

initial 
begin
   clk =0;
   rst_l = 0;
   sw_rst= 0;
   fifo_push_en=0;
   fifo_pop_en=0;
   fifo_din=0;
   tempdata=0;

   #15 rst_l=1;
   #1  sw_rst=1;

   push(10);
   push(20);
   push(30);
   push(40);
   pop(tempdata);
   push(tempdata);


end

always 
   #5 clk=~clk;


task push;
   input[`WIDTH-1:0] data;
   if(fifo_o_full) 
      $display("--- Cannot push: Buffer full ----");
    else begin 
      $display("Pushed: ",data);
      @(posedge clk);
      fifo_din = data;
      fifo_push_en=1;
      @(posedge clk);
      fifo_push_en=0;
   end
endtask

task pop;
   output [`WIDTH-1:0] data;

   if(fifo_o_empty) 
      $display("Cannot pop: buffer empty ---");
      else begin
         @(posedge clk);
         fifo_pop_en=1;
         @(posedge clk);
         fifo_pop_en=0;
         data=fifo_dout;
         $display("----- Poped : ",data);
      end
 endtask


 endmodule

Answer 1

抛开与指针递增相关的奇怪之处不谈，代码本身是令人困惑和难以处理的。粘贴引用FIFO模块应该做的工作，这也应该帮助你掌握编码风格的基础知识。

//----------------------------------------------------
// Module Name: fifo_sync.v
//----------------------------------------------------
// Description: generic sync FIFO module
//----------------------------------------------------

module fifo_sync #
(
    parameter FIFO_DATA_WIDTH = 'd32,
    parameter FIFO_PTR_WIDTH = 'd6
)
(
    //------------------------------------------------
    // Inputs
    //------------------------------------------------
    input                       clk,
    input                       rst_n,
    input                       wr_en,
    input [FIFO_DATA_WIDTH-1:0] wr_data,
    input                       rd_en,

    //------------------------------------------------
    // Outputs
    //------------------------------------------------
    output reg [FIFO_DATA_WIDTH-1:0] rd_data,
    output                           stat_full,
    output                           stat_empty,
    output     [ FIFO_PTR_WIDTH-1:0] stat_occupancy
);

    //------------------------------------------------
    // Local Parameters
    //------------------------------------------------
    localparam FIFO_DEPTH = 2**(FIFO_PTR_WIDTH-1);

    //------------------------------------------------
    // Internal Register(s)/Wire(s)/Integer(s)
    //------------------------------------------------
    reg [ FIFO_PTR_WIDTH-1:0] wr_ptr;
    reg [ FIFO_PTR_WIDTH-1:0] rd_ptr;
    reg [FIFO_DATA_WIDTH-1:0] fifo_array [FIFO_DEPTH-1:0];
    integer int_i;

    //------------------------------------------------
    // Write Pointer Logic
    //------------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_wr_ptr
        if (!rst_n)
            wr_ptr <= {FIFO_PTR_WIDTH{1'b0}};
        else if (wr_en & !stat_full)
            wr_ptr <= wr_ptr + 1'b1;
    end

    //------------------------------------------------
    // Read Pointer Logic
    //------------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_rd_ptr
        if (!rst_n)
            rd_ptr <= {FIFO_PTR_WIDTH{1'b0}};
        else if (rd_en & !stat_empty)
            rd_ptr <= rd_ptr + 1'b1;
    end

    //------------------------------------------------
    // Status Interface
    //------------------------------------------------

    // FIFO full status flag
    assign stat_full = (wr_ptr[FIFO_PTR_WIDTH-1] ^ rd_ptr[FIFO_PTR_WIDTH-1]) & (wr_ptr[FIFO_PTR_WIDTH-2:0] == rd_ptr[FIFO_PTR_WIDTH-2:0]);
    // FIFO empty status flag
    assign stat_empty = (wr_ptr == rd_ptr);
    // FIFO occupancy status
    assign stat_occupancy = wr_ptr - rd_ptr;

    //-----------------------------------------------
    // FIFO Write
    //-----------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_fifo_write
        if (!rst_n)
            for (int_i = 0; int_i < FIFO_DEPTH - 1; int_i = int_i + 1)
                fifo_array[int_i] <= {FIFO_DATA_WIDTH{1'b0}};
        else if (wr_en & !stat_full)
            fifo_array[wr_ptr] <= wr_data;
    end

    //-----------------------------------------------
    // FIFO Read
    //-----------------------------------------------
    always @(posedge clk or negedge rst_n)
    begin: p_fifo_read
        if (!rst_n)
            rd_data <= {FIFO_DATA_WIDTH{1'b0}};
        else if (rd_en & !stat_empty)
            rd_data <= fifo_array[rd_ptr];
    end

endmodule