有结构VHDL的ALU？

Question

我试图用VHDL中的结构代码创建一个ALU。代码最初是用Verilog编写的，然后我手动将其更改为VHDL，这就是为什么理论上我有许多独立的files...but，它们应该可以工作。以下是相关的代码和文件：

-dwl_fulladd代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_fulladd IS
    PORT    (   
            x, y, Cin:      IN STD_LOGIC;
            s, Cout:            OUT STD_LOGIC);
END dwl_fulladd;

ARCHITECTURE Structural OF dwl_fulladd IS

BEGIN
    s <= x XNOR y XNOR Cin;
    Cout <= ((x AND y) OR (x AND Cin) OR (y AND Cin));
END Structural;

-dwl_4加法器代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_4bitadder IS
    PORT    (   
            x, y :      IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryin:    IN STD_LOGIC;
            s:              OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryout:   OUT STD_LOGIC);
END dwl_4bitadder;

ARCHITECTURE Structural OF dwl_4bitadder IS

SIGNAL c : STD_LOGIC_VECTOR (3 DOWNTO 1);

COMPONENT dwl_fulladd
    PORT    (   
            x, y, Cin:      IN STD_LOGIC;
            s, Cout:            OUT STD_LOGIC);
END COMPONENT dwl_fulladd;


BEGIN
stage0: dwl_fulladd PORT MAP (carryin, x(0), y(0), s(0), c(1));
stage1: dwl_fulladd PORT MAP (c(1), x(1), y(1), s(1), c(2));
stage2: dwl_fulladd PORT MAP (c(2), x(2), y(2), s(2), c(3));
stage3: dwl_fulladd PORT MAP (c(3), x(3), y(3), s(3), carryout);

END Structural;

-dwl_mux2to1代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_mux2to1 IS
PORT    (   
            x1, x2, s:      IN STD_LOGIC;
            f:                  OUT STD_LOGIC);
END dwl_mux2to1;

ARCHITECTURE Structural OF dwl_mux2to1 IS

BEGIN
f <= (((NOT s)AND x1)OR(s AND x2));

END Structural;

-dwl_4mux2to1码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_4mux2to1 IS
PORT    (   
            x0, x1: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            sel:        IN STD_LOGIC;
            f:          OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END dwl_4mux2to1;

ARCHITECTURE Structural OF dwl_4mux2to1 IS

COMPONENT dwl_mux2to1 IS
PORT    (   
            x1, x2, s:      IN STD_LOGIC;
            f:                  OUT STD_LOGIC);
END COMPONENT dwl_mux2to1;

BEGIN
stage0: dwl_mux2to1 PORT MAP (sel, x0(0), x1(0), f(0));
stage1: dwl_mux2to1 PORT MAP (sel, x0(1), x1(1), f(1));
stage2: dwl_mux2to1 PORT MAP (sel, x0(2), x1(2), f(2));
stage3: dwl_mux2to1 PORT MAP (sel, x0(3), x1(3), f(3));

END Structural;

-dwl_Blogic代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_Blogic IS
PORT    (   
            FS2_in, FS1_in: IN STD_LOGIC;
            B_in:                   IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            Y_out:              OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

END dwl_Blogic;

ARCHITECTURE Behavioral OF dwl_Blogic IS

BEGIN
PROCESS (FS2_in, FS1_in, B_in)
BEGIN
if FS2_in = '0' AND FS1_in = '0' then
    Y_out <= "0000";
elsif FS2_in = '0' AND FS1_in = '1' then
    Y_out <= B_in;
elsif FS2_in = '1' AND FS1_in = '0' then
    Y_out <= (NOT B_in);
elsif FS2_in = '1' AND FS1_in = '1' then
    Y_out <= "1111";
end if;
END PROCESS;

END Behavioral;

-dwl_lu代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_lu IS
PORT    (   
            FS:         IN STD_LOGIC_VECTOR (2 DOWNTO 1);
            A, B:           IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            lu_out:     OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryout:   OUT STD_LOGIC);
END dwl_lu;

ARCHITECTURE Behavioral OF dwl_lu IS

BEGIN
PROCESS (FS, A, B)
BEGIN
if FS = "00" then
    lu_out <= (Not A);
    carryout <= '0';
elsif FS = "01" then
    lu_out <= (A AND B);
    carryout <= '0';
elsif FS = "10" then
    lu_out <= (A OR B);
    carryout <= '0';
elsif FS = "11" then
    lu_out <= (A(3) & A(3) & A(2) & A(1));
    carryout <= A(0);
END if;
END PROCESS;

END Behavioral;

-dwl_au代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_au IS
PORT    (   
            FS:         IN STD_LOGIC_VECTOR (2 DOWNTO 0);
            A, B:           IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            au_out:     OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryout:   OUT STD_LOGIC);
END dwl_au;

ARCHITECTURE Structural OF dwl_au IS

SIGNAL Y: STD_LOGIC_VECTOR (3 DOWNTO 0);

COMPONENT dwl_Blogic IS
PORT    (   
            FS2_in, FS1_in: IN STD_LOGIC;
            B_in:                   IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            Y_out:              OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

END COMPONENT dwl_Blogic;

COMPONENT dwl_4bitadder IS
PORT    (   
            x, y :      IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryin:    IN STD_LOGIC;
            s:              OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryout:   OUT STD_LOGIC);
END COMPONENT dwl_4bitadder;

BEGIN
stage0: dwl_Blogic (FS(2), FS(1), B, Y);
stage1: dwl_4bitadder (FS(0), A, Y, au_out, carryout);

END Structural;

-dwl_alu代码--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY dwl_alu_vhdl IS
PORT    (   
            FS, A, B:           IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            F:                      OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            Cout:                   OUT STD_LOGIC);
END dwl_alu_vhdl;

ARCHITECTURE Structural OF dwl_alu_vhdl IS

SIGNAL AU, LU: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL AU_C, LU_C: STD_LOGIC;

COMPONENT dwl_au IS
PORT    (   
            FS:         IN STD_LOGIC_VECTOR (2 DOWNTO 0);
            A, B:           IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            au_out:     OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryout:   OUT STD_LOGIC);
END COMPONENT dwl_au;

COMPONENT dwl_lu IS
PORT    (   
            FS:         IN STD_LOGIC_VECTOR (2 DOWNTO 1);
            A, B:           IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            lu_out:     OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
            carryout:   OUT STD_LOGIC);
END COMPONENT dwl_lu;

COMPONENT dwl_4mux2to1 IS
PORT    (   
            x0, x1: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            sel:        IN STD_LOGIC;
            f:          OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT dwl_4mux2to1;

COMPONENT dwl_mux2to1 IS
PORT    (   
            x1, x2, s:      IN STD_LOGIC;
            f:                  OUT STD_LOGIC);
END COMPONENT dwl_mux2to1;

BEGIN
stage0: dwl_au (FS(2 DOWNTO 0), A, B, AU, AU_C);
stage1: dwl_lu (FS(2 DOWNTO 1), A, B, LU, LU_C);
stage2: dwl_4mux2to1 (FS(3), AU, LU, F);
stage3: dwl_mux2to1 (FS(3), AU_C, LU_C, Cout);

 END Structural;

这是逻辑单元的真值表：逻辑

这是BLogic单元的真值表：在这里输入图像描述

我不断地发现以下错误：

Error (10777): VHDL error at nwl_au.vhd(34): expected an architecture     identifier in index.

Error (10346): VHDL error at nwl_au.vhd(34): formal port or parameter "FS2_in" must have actual or default value.

Error (10784): HDL error at nwl_au.vhd(19): see declaration for object "FS2_in".

Error (10346): VHDL error at nwl_au.vhd(34): formal port or parameter "FS1_in" must have actual or default value.

Error (10784): HDL error at nwl_au.vhd(19): see declaration for object "FS1_in".

Error (10346): VHDL error at nwl_au.vhd(34): formal port or parameter "B_in" must have actual or default value.

Error (10784): HDL error at nwl_au.vhd(20): see declaration for object "B_in".

这些错误与代码的dwl_au诗歌有关。

有人能帮上忙吗？我不知道怎么修好它。

Answer 1

您的代码有两处错误：

i)您的实例化语法缺少构造port map。这

stage0: dwl_Blogic (FS(2), FS(1), B, Y);
stage1: dwl_4bitadder  (A, Y, FS(0),  au_out, carryout);

应该是这样：

stage0: dwl_Blogic port map (FS(2), FS(1), B, Y);
stage1: dwl_4bitadder port map  (A, Y, FS(0),  au_out, carryout);

这是：

stage0: dwl_au (FS(2 DOWNTO 0), A, B, AU, AU_C);
stage1: dwl_lu (FS(2 DOWNTO 1), A, B, LU, LU_C);
stage2: dwl_4mux2to1 ( AU, LU, FS(3), F);
stage3: dwl_mux2to1 (FS(3), AU_C, LU_C, Cout);

应该是这样：

stage0: dwl_au port map (FS(2 DOWNTO 0), A, B, AU, AU_C);
stage1: dwl_lu port map (FS(2 DOWNTO 1), A, B, LU, LU_C);
stage2: dwl_4mux2to1 port map ( AU, LU, FS(3), F);
stage3: dwl_mux2to1 port map (FS(3), AU_C, LU_C, Cout);

( ii)您在港口地图中使用位置关联会导致两个错误。基本上，您没有正确连接端口。因此，例如，它没有正确连接(我知道是因为它没有编译)：

stage1: dwl_4bitadder (FS(0), A, Y, au_out, carryout);

我的猜测(因为在端口类型上)是指：

stage1: dwl_4bitadder (A, Y, FS(0), au_out, carryout);

但只有你知道这是否正确。但是(这是非常重要的)，如果您在端口映射中使用了命名关联，那么您可能不会犯这样的错误。因此，与以上所述不同，(我并不知道您的设计意图，因此可能会出错)，请执行以下操作：

stage1: dwl_4bitadder (x => A, y => Y, carryin => FS(0), s => au_out, carryout => carryout);

从不为端口映射使用位置关联。它太容易出错，正如您的代码所演示的那样。