生成VHDL双端口RAM意外锁存

Question

我为我的16位MIPS架构写了一个寄存器文件，这里我确保我的register0包含所有的零，没有语法错误，但是我有一些问题。

1. 我做好打字了吗？因为我收到了一些关于生成闩锁的警告。我在这里做错了什么？
2. 另外，conv_integer和to_integer(无符号((W_addr))有什么区别？因为当我使用to_integer(无符号(R_addr1)=0)时，我遇到了错误。 库IEEE；使用IEEE.STD_LOGIC_1164.ALL；使用IEEE.std_logic_unsigned.all；使用IEEE.NUMERIC_STD.ALL；实体重新文件是通用的( N: integer:=4；-地址W的位数: integer:=16 -位数)；端口( clk : in STD_LOGIC；w_en : in STD_LOGIC；r_addr1、r_addr2、w_addr : in STD_LOGIC_VECTOR (N-1下降到0)；w_data: STD_LOGIC_VECTOR (W-1降至0)；r_data1，r_data2 : out STD_LOGIC_VECTOR (W-1降至0)；end regfile；regfile_type的体系结构行为是STD_LOGIC_VECTOR的数组(W-1降至0)；信号RegisterFile: regfile_type；开始进程(clk )开始if (clk= '1')然后if (w_en = '1')然后RegisterFile(to_integer(无符号(W_addr)) <= w_data；end if；end if；end process；process (r_addr1，r_addr2)开始if (conv_integer(r_addr1)=0)，然后r_data1 <= X"0000"；否则r_data1<=RegisterFile(to_integer(unsigned(r_addr1)))；结束if；if (conv_integer(r_addr2)=0)然后r_data2 <= X"0000"；否则r_data2 <= RegisterFile(to_integer(无符号(R_addr2)；结束if；结束过程；结束行为；

这些是我收到的警告

WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<w_en>, <w_data>
WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 58: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <RegisterFile>
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Answer 1

1.行：

if (clk = '1') then

应当是：

if (clk'event and clk = '1') then

或者：

if rising_edge(clk) then

这就是创建锁锁的地方。虽然事件似乎应该被敏感性列表所暗示，但它需要明确的综合工具来正确地推断一个触发器。

2. to_integer(unsigned(r_addr1)=0) --你的意思是to_integer(unsigned(r_addr1))=0 (哪个应该工作得很好)？注意与括号相匹配。顺便说一句，unsigned将其与整数字面值进行了比较，因此这里不需要to_integer。只要unsigned(r_addr1)=0就行了。

Answer 2

您的时钟进程写得不正确。工具没有意识到clk实际上是一个时钟。您需要使用clk‘’event，或者更好地使用rising_edge()。这些工具正在创建一个组合过程，而不是一个连续的过程。因为if语句没有其他条件，所以它使RegisterFile成为锁存器。以下是关于什么是锁存器以及如何避免FPGA中的锁存。的更多信息

process(clk)
begin
  if rising_edge(clk) then
    if w_en = '1' then
      RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
    end if;
  end if;
end process;