泛型记录(试图通过vhdl 2008通用程序包)

Question

我想为组件C编写一个库，该组件在内部被分成两个超级组件c1和c2，它们是由泛型配置的。子模块应该由一个记录连接，这取决于泛型。记录也应在组件中使用。通常，我会在package中实例化记录，并在子组件的文件中和组件的文件中使用包。因为它是通用的，所以我认为使用泛型包(VHDL-2008)可能会提供一个解决方案。

问题是，我还需要从子组件中访问记录。要做到这一点，我需要use thePackage，但是要使用泛型包，我需要传递初始值(据我所知)。

因此，我尝试了(注意:我不在这里处理记录，我只是尝试从泛型组件访问泛型包，其中我参数化了(？)包含组件参数的包)：

entity genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
end entity;

architecture behav of genericPackagePart is
    package test is new work.genericPackage
    generic map(
        genSize => outputValue
    );

    use work.test.all;
begin
    result <= dummy;  -- dummy is a constant from genericPackage set to the value genSize (generic parameter)
end architecture;

但是，我从modelsim中得到以下错误：

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(17): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(17): Unknown expanded name.
** Error: genericPackagePart.vhd(19): (vcom-1136) Unknown identifier "dummy".
** Error: genericPackagePart.vhd(20): VHDL Compiler exiting

更新：--我尝试将genericPackagePart包装在一个泛型包中，并从该包中用泛型实例化genericPackage，这也不起作用。

流量应该是：

• Testbench =>用泛型参数实例化genericPackagePart和genericPackage
• 该记录可从genericPackage的testbench中获得。
• 在genericPackagePart内部，使用传递给genericPackagePart的参数实例化genericPackage
• 该记录可在genericPackagePart中使用

Modelsim给出了错误(test是genericPackage在genericPackagePart中参数化实例的名称，这来自于genericPackagePart的编译)：

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(11): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(11): Unknown expanded name.
** Error: genericPackagePart.vhd(13): near "entity": expecting END

我看过Passing Generics to Record Port Types，但这并不能解决基于泛型的包实例化问题。

为了实现完整，这里有一个包和一个测试平台：

包：

package genericPackage is
    generic(genSize : integer := 1);

    constant dummy : integer := genSize;
end package;

测试平台：

package myGenericPackage is new work.genericPackage
generic map(
    genSize => 5
);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal : integer;
    signal testsignal2 : integer;
    signal dummy : integer := 12;

    component genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
    end component;
begin
    test : process is
    begin
        wait for 20 ns;
        testsignal <= dummy;
        wait for 20 ns;
        testsignal <= work.myGenericPackage.dummy;
        wait;
    end process;

    testPart: genericPackagePart
        port map(result => testsignal2)
        generic map(outputValue => 128);
end architecture;

Answer 1

我认为问题在于您的包test需要在实体区域而不是体系结构区域中定义：

package genericPackage is
    generic(genSize : integer := 1);
    constant dummy : integer := genSize;
end package;
entity genericPackagePart is
    generic(outputValue : integer);
    port(result : out integer);

    -- *** Generic package instantiated here ***
    package test is new work.genericPackage
       generic map(genSize => outputValue);

end entity;
architecture behav of genericPackagePart is
    use test.all;
begin
    result <= dummy;  -- dummy is from genericPackage (=genSize)
end architecture;

下面是我如何测试它(基于您的testbench)：

package myGenericPackage is new work.genericPackage
   generic map(genSize => 5);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal  : integer;
    signal testsignal2 : integer;
begin
    test : process is
    begin
        testsignal <= work.myGenericPackage.dummy;
        wait for 20 ns;

        assert testsignal = work.myGenericPackage.dummy 
            report "test signal should be work.myGenericPackage.dummy" 
            severity error;
        assert testsignal2 = 128 report "testsignal2 /= 128" severity error;
        report "testsignal = " & integer'image(testsignal);
        report "testsignal2 = " & integer'image(testsignal2);
        report "Finished";
        wait;
    end process;

    testPart : entity work.genericPackagePart
        generic map(outputValue => 128)
        port map(result         => testsignal2);
end architecture;

用Modelsim 10.2编译并模拟：

vcom -2008 genpacktest.vhd; vsim -c genericPackageTestbench -do "run -all; quit"

其中报告：

# Loading std.standard
# Loading work.genericpackage
# Loading work.mygenericpackage
# Loading work.genericpackagetestbench(testbench)
# Loading work.genericpackagepart(behav)
# run -all 
# ** Note: Finished
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal = 5
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal2 = 128
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
#  quit