如何将AHB端口连接到DRAM控制器设备上

Question

如何从火箭芯片连接到外部的AHB从端口(即内存控制器上的AHB端口)？在其他几个连接到AXI4从设备的示例之后，我尝试了格式化我的代码，这些示例运行良好。但是，当我尝试实现相同的方法时，:=高亮显示为IntelliJ中的红色squigglies，这告诉我它无法连接这两种类型的节点，或者类与绑定操作不兼容。我觉得我错过了关于这些节点类型的一些重要概念，这些节点类型涉及如何将这些设备粘合在一起。

trait CanHaveDdr4Ahb extends LazyModule { this: BaseSubsystem =>

  import freechips.rocketchip.subsystem.ExtMem

  override val module: CanHaveDdr4AhbImp

  val ahb_mem = p(ExtMem).map {
    case MemoryPortParams(mpp, nChan) => {
    val portName = "my_ahb"
    val device = new MemoryDevice
    val memAHBNode = AHBSlaveSinkNode(Seq.tabulate(nChan) { channel =>
      val base = AddressSet.misaligned(mpp.base, mpp.size)
      val filter = AddressSet(channel * mbus.blockBytes, ~((nChan - 1) * mbus.blockBytes))

      AHBSlavePortParameters(
        slaves = Seq(AHBSlaveParameters(
          address = List(AddressSet(mpp.base, mpp.size - 1)),
          resources = device.reg,
          regionType = RegionType.UNCACHED,
          executable = true,
          supportsWrite = TransferSizes(1, mbus.blockBytes),
          supportsRead = TransferSizes(1, mbus.blockBytes))),
        beatBytes = mpp.beatBytes)
    })

// TODO: Why can't I assign DRAMController output to this AHBSlaveSinkNode?
// AHBSlaveSinkNode := OutwardNodeHandle[D,U,E,B] { body }
    memAHBNode := mbus.toDRAMController(Some(portName)) { TLToAHB() }
    memAHBNode
  }
}

编辑： of，在获得代码库后，返回Chipyard并使用所给出的解决方案，即删除AHBSlaveParameters中nodePath和设备的赋值，并将:=绑定语句更改为：

memAHBNode := mbus.toDRAMController(Some(portName)) { TLToAHB() }

..。相同类型的错误仍然存在，即处理bind操作如何尝试绑定到左侧的某项内容的内容：

  OutwardNodeHandle[
    AHBMasterPortParameters, 
    AHBSlavePortParameters, 
    AHBEdgeParameters, 
    AHBMasterBundle] // <-- should be AHBSlaveBundle according to ahb/Nodes.scala

注意，在最后一行中，它试图匹配

OutwardNodeHandle[D,U,E,AHBSlaveBundle]

关于RHS的推断

OutwardNodeHandle[D,U,E,AHBMasterBundle]

在任务的LHS上。我不知道为什么编译器会那样输入它。下面是我得到的错误输出。我还更新了上面的代码。

[error] /home/abryant/workspace/chipyard/generators/socta1_rtl/src/main/scala/devices/Ddr4Ahb.scala:62:16: overloaded method value := with alternatives:
[error]   [EY](h: freechips.rocketchip.diplomacy.OutwardNodeHandle[freechips.rocketchip.amba.ahb.AHBMasterPortParameters,freechips.rocketchip.amba.ahb.AHBSlavePortParameters,EY,freechips.rocketchip.amba.ahb.AHBSlaveBundle])(implicit p: freechips.rocketchip.config.Parameters, implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)freechips.rocketchip.diplomacy.OutwardNodeHandle[freechips.rocketchip.amba.ahb.AHBMasterPortParameters,freechips.rocketchip.amba.ahb.AHBSlavePortParameters,freechips.rocketchip.amba.ahb.AHBEdgeParameters,freechips.rocketchip.amba.ahb.AHBSlaveBundle] <and>
[error]   [DX, UX, EX, BX <: Chisel.Data, EY](h: freechips.rocketchip.diplomacy.NodeHandle[DX,UX,EX,BX,freechips.rocketchip.amba.ahb.AHBMasterPortParameters,freechips.rocketchip.amba.ahb.AHBSlavePortParameters,EY,freechips.rocketchip.amba.ahb.AHBSlaveBundle])(implicit p: freechips.rocketchip.config.Parameters, implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)freechips.rocketchip.diplomacy.NodeHandle[DX,UX,EX,BX,freechips.rocketchip.amba.ahb.AHBMasterPortParameters,freechips.rocketchip.amba.ahb.AHBSlavePortParameters,freechips.rocketchip.amba.ahb.AHBEdgeParameters,freechips.rocketchip.amba.ahb.AHBSlaveBundle]
[error]  cannot be applied to (freechips.rocketchip.diplomacy.OutwardNodeHandle[freechips.rocketchip.amba.ahb.AHBMasterPortParameters,freechips.rocketchip.amba.ahb.AHBSlavePortParameters,freechips.rocketchip.amba.ahb.AHBEdgeParameters,freechips.rocketchip.amba.ahb.AHBMasterBundle])
[error]     memAHBNode := mbus.toDRAMController(Some(portName)) {
[error]                ^

mbus.toDRAMController传递给:=的：=可以从AXI4Slave类型继承，但不能从AHBSlave类型继承。

Answer 1

试试这个：

          memAHBNode := mbus.toDRAMController(Some(portName)) { TLToAHB() }

你让事情变得太复杂了。:-)

您也不应该在nodePath或device字段中设置AHBSlavePortParamters。坦率地说，我对device的存在感到震惊，并且应该尽快删除它。

Answer 2

最后，在对scala代码进行了一周的研究之后，我完成了这个问题：

Ports.scala

case object ExtMem1 extends Field[Option[MemoryPortParams]](None)

trait CanHaveMasterAHBMemPort {
  this: BaseSubsystem =>
  val module: CanHaveMasterAHBMemPortModuleImp

  val mem1_ahb_node = p(ExtMem1).map { case MemoryPortParams(memPortParams, nMemoryChannels) =>
    val portName = "ahbMem"
    val device = new MemoryDevice

    val mem1_AHB_node = AHBMasterSinkNode(Seq.tabulate(nMemoryChannels) { channel =>
    val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
    val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))

      AHBSlavePortParameters(
        slaves = Seq(AHBSlaveParameters(
          //address = AddressSet.misaligned(memPortParams.base, memPortParams.size),
          address       = base.flatMap(_.intersect(filter)),
          resources     = device.reg,
          regionType = RegionType.UNCACHED, // cacheable
          executable = true,
          supportsWrite = TransferSizes(1, mbus.blockBytes),
          supportsRead  = TransferSizes(1, mbus.blockBytes))),
        beatBytes = memPortParams.beatBytes,
        lite = true)
    })

    mem1_AHB_node := mbus.toDRAMController(Some(portName)) {
      AHBLite() := TLToAHB()
    }
    mem1_AHB_node
  }
}

我使用的是带有散列4f0cdea85c8a2b849fd582ccc8497892001d06b0 B的2019年10月20日的火箭芯片