不更新VHDL LR移位器循环

Question

我这里有我的代码，但是当我运行TB时，当我离开左边='1‘的时候，我的移位不能工作，而时钟有另一个上升的边缘。

这里的目标是制作一个左、右平行移位寄存器。登记册必须更新每一个上升的边缘时钟。当le高时，它加载信息，当左高时，它应该做左循环移位。如果权利是高的，它应该做正确的循环移位。

寄存器的表解释功能我做错什么了？

---------------------------------------------------------
-- Description: 
--  An n-bit register (parallel in and out) with left and right shift
--  functionality (circular).
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lr_shift_par_load is
    generic(
        C_REG_WIDTH : natural := 8
    );
    port(
          reset : in  STD_LOGIC;
            clk : in  STD_LOGIC;
           left : in  STD_LOGIC;
          right : in  STD_LOGIC;
             le : in  STD_LOGIC;
         par_in : in  STD_LOGIC_VECTOR(C_REG_WIDTH-1 downto 0);
        par_out : out STD_LOGIC_VECTOR(C_REG_WIDTH-1 downto 0)
    );
end lr_shift_par_load;

architecture Behavioral of lr_shift_par_load is

    signal reg_i : std_logic_vector(C_REG_WIDTH-1 downto 0) := (others=>'0');
begin

    -- TODO: Write a process that implements the correct behaviour for reg_i.
    --   This should be a good refresher of your knowledge of last year.
    process(clk,reset)
    begin
        if(reset = '1')then
            reg_i <= (others=>'0');
        end if;
        if(rising_edge(clk)) then
            if(le ='1') then
                -- load
                reg_i <= par_in;
            elsif(le ='0' and left ='1')then 
                -- shift left
                reg_i <= par_in(C_REG_WIDTH-2 downto 0) &  par_in(C_REG_WIDTH-1);
            elsif(le ='0' and left ='0'and right ='1')then
                -- shift right
                reg_i <= par_in(0) & par_in(C_REG_WIDTH-1 downto 1);
            elsif(le ='0' and left ='0'and right ='0')then
                --hold
                reg_i <= par_in;
            end if;
        end if;
     end process;

    par_out <= reg_i;

end Behavioral;

Answer 1

在移位时，使用输入向量“par_in”。您可能希望使用shift寄存器本身：'reg_i‘。

而且，你的条件是不必要的复杂。

 if(le ='1') then
    -- load
     reg_i <= par_in;
 elsif(le ='0' ... << Why are you testing for this? 
                      If "le" was not zero it would never get here 
                      but get handled in the first 'if'.

这里也是如此：

(le ='0' and left ='0'and right ='1') then

(le ='0' and left ='0'是超快的。