维里罗格未签名不恢复师。语法错误：“我放弃”Icarus Verilog

Question

我想知道为什么我的Iverilog编译器在模块的末尾抛出“我放弃”错误。错误是：

DivisionsSchaltwerk.v:64:语法错误我放弃了

有Verilog代码为我的分区使用了一个修改版本的AQ移位，无符号，不恢复除法算法。第64列位于endmodule部分。

module Division(
    input         clock,
    input         start,
    input  [31:0] a,
    input  [31:0] b,
    output [31:0] q,
    output [31:0] r
);
    reg[31:0] AQ;
    reg[31:0] B;
    reg[31:0] R;
    reg[5:0] count;
    reg running;

    assign q = AQ;
    assign r = R;
    
    always @(posedge clock) begin
        if (start) begin
            R <= 0;
            AQ <= a;
            B <= b;
            count <= 6'd32;
            running <= 1;
         end
        else if (count == 0) begin
            running <=0;
            if(R<0) begin
                R <= R + B;
            end
            else begin
                R <= R - B;
            end
        end
        if (running) begin
            if (R<0) begin
                R <= R<<1;
                R[0] <= AQ[32];
                AQ <= AQ<<1;
            end
               if(R<0) begin 
                    AQ[0] <= 0;
                    R <= R + B;
                    count <= count -6'd1;
                end
                else begin
                    AQ[0] <= 1;
                    R <= R - B;
                    count <= count - 6'd1;
                end
            end
            else begin
                R <= R<<1;
                R[0] <= AQ[32];
                AQ <= AQ<<1;
            end
                if(R<0) begin 
                    AQ[0] <= 0;
                    R <= R + B;
                    count <= count -6'd1;
                end
                else begin
                    AQ[0] <= 1;
                    R <= R - B;
                    count <= count - 6'd1;
                end                
endmodule

Answer 1

代码有两种类型的错误：

1. 编译错误
2. 编译警告

编译错误是end块中缺少的always。其他模拟器(如edaplayground，上的模拟器)会产生更有用(也更常见)的错误消息，如：

endmodule
        |
xmvlog: *E,NOTSTT : expecting a statement [9(IEEE)].

再加上代码的不一致缩进，这通常意味着不匹配的begin/end对。此外，您可以使用emacs自动重新缩进代码：

emacs --batch DivisionsSchaltwerk.v -f verilog-batch-indent 

您还会得到编译警告，如：

            R[0] <= AQ[32];
                     |
xmelab: *W,BNDWRN : Bit-select or part-select index out of declared bounds.

您将AQ声明为31:0。你真的想用AQ[31]

下面是带有匹配always的自动缩进begin/end块

   always @(posedge clock) begin
      if (start) begin
         R <= 0;
         AQ <= a;
         B <= b;
         count <= 6'd32;
         running <= 1;
      end
      else if (count == 0) begin
         running <=0;
         if(R<0) begin
            R <= R + B;
         end
         else begin
            R <= R - B;
         end
      end
      if (running) begin
         if (R<0) begin
            R <= R<<1;
            R[0] <= AQ[32];
            AQ <= AQ<<1;
         end
         if(R<0) begin 
            AQ[0] <= 0;
            R <= R + B;
            count <= count -6'd1;
         end
         else begin
            AQ[0] <= 1;
            R <= R - B;
            count <= count - 6'd1;
         end
      end
      else begin
         R <= R<<1;
         R[0] <= AQ[32];
         AQ <= AQ<<1;
      end
      if(R<0) begin 
         AQ[0] <= 0;
         R <= R + B;
         count <= count -6'd1;
      end
      else begin
         AQ[0] <= 1;
         R <= R - B;
         count <= count - 6'd1;
      end                
   end

Answer 2

您的代码有12个“开始”和11个“结束”单词。试着纠正缩进，以找出缺失的“结束”。