不同的结构元素“由连续的和程序性的任务编写”

Question

我为什么要：

# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[0]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[1]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[2]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[3]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[0]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[1]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[2]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[3]' written by continuous and procedural assignments. See testbench.sv(19). 

对于此代码：

module tb;

logic clk;

struct {
  struct {
    logic seq;
    logic assig;
    logic seq2;
  } subar [4];
} ar [2];


always_ff @(posedge clk) begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].seq <= '1;
    end
  end
end

generate
  for (genvar i=0; i<2; i++) begin
    for (genvar j=0; j<4; j++) begin
      assign ar[i].subar[j].assig = '1;
    end
  end
endgenerate

always_ff @(posedge clk) begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].seq2 <= '1;
    end
  end
end

endmodule

这三种逻辑在结构内部是相互独立的，它们不被分配在两个不同的块中。

EDA游乐场：https://www.edaplayground.com/x/qYZ9

用always_comb替换生成/赋值

always_comb begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].assig = ar[i].subar[j].seq;
    end
  end
end

用一个assign块替换generate会产生不同的结果，因为所有的*.seq信号都是X。

每个assig = seq在每个i和j迭代之间都是独立的。

为什么这个无效？

不能用结构来分组信号是非常烦人的.

Answer 1

错误消息是因为IEEE1801-2017 SystemVerilog LRM第11.5.3节对最长静态前缀的定义相当悲观。基本上，因为i是一个变量索引，所以ar[i]的长静态前缀是ar，任何数组或结构都会选择不相关的继承。工具一直对此持更乐观的态度，但这是一个渐进的过程。

您可以全局地抑制错误，或者重写将for循环从块中移出的代码到generate-for循环中。

module tb;

logic clk;

struct {
  struct {
    logic seq;
    logic assig;
    logic seq2;
  } subar [4];
} ar [2];

for (genvar  i=0; i<2; i++) begin
  for (genvar  j=0; j<4; j++) begin
always_ff @(posedge clk) begin
      ar[i].subar[j].seq <= '1;
    end
  end
end

  for (genvar i=0; i<2; i++) begin
    for (genvar j=0; j<4; j++) begin
      assign ar[i].subar[j].assig = '1;
    end
  end

for (genvar  i=0; i<2; i++) begin
  for (genvar  j=0; j<4; j++) begin
    always_ff @(posedge clk) begin
      ar[i].subar[j].seq2 <= '1;
    end
  end
end

endmodule