VHDL能合成clk事件吗？

Question

我正在尝试用VHDL写一个4位乘法器。这是我写的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier_8bit_2 is
    Port ( clk : in  STD_LOGIC;
           A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (7 downto 0));
end multiplier_8bit_2;

architecture Behavioral of multiplier_8bit_2 is

begin
process(clk, A, B)
    variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
    if A'event or B'event then
        sum_result:=(others => '0');
        for i in 0 to 3 loop
            if B(i)='1' then
                sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
            end if;
        end loop;
    end if;
    Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;

end Behavioral;

它可以在模拟中执行，并且可以工作，但当我尝试合成它时，我得到: unsupported时钟语句。

Answer 1

如果你只想要一个带有4位参数的乘法器，那么可以不使用clk进行编码，如下所示。您不需要a‘’event‘或b’‘event。

process(A, B)
    variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
    sum_result:=(others => '0');
    for i in 0 to 3 loop
        if B(i)='1' then
           sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
        end if;
    end loop;
    Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;

OTOH，如果你想要一个乘法器和一个触发器，那么编写以下代码。您不需要在敏感度列表中使用A或B。

process(clk)
    variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
    if clk = '1' and clk'event then
        sum_result:=(others => '0');
        for i in 0 to 3 loop
            if B(i)='1' then
                sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
            end if;
        end loop;
        Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
    end if;
end process;