chisel3中的BlackBox功能

Question

我想尝试一下chisel中的BlackBox功能，但我得到了以下警告信息，无法通过峰/戳测试：

Total FIRRTL Compile Time: 237.8 ms
WARNING: external module "BlackBoxSwap"(swap:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
WARNING: external module "BlackBoxSwap"(:BlackBoxSwap)was not matched with an implementation
file loaded in 0.398085417 seconds, 25 symbols, 15 statements

源码如下: gcd包

import chisel3._
import chisel3.util._

class BlackBoxSwap extends BlackBox with HasBlackBoxInline  {
//class BlackBoxRealSwap extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle() {
    //val clk = Input(Clock())
      //val reset = Input(Bool())
    val out2 = Output(UInt(16.W))
    val out1 = Output(UInt(16.W))
    val in2 = Input(UInt(16.W))
    val in1 = Input(UInt(16.W))
  })


  //setResource("/real_swap.v")

  setInline("BlackBoxSwap.v",
    s"""
       |module BlackBoxSwap (
       |  input  [15:0] in1,
       |  input  [15:0] in2,
       |  output [15:0] out1,
       |  output [15:0] out2
       |);
       |
       |assign out1 = in2;
       |assign out2 = in1;
       |
       |endmodule
    """.stripMargin)

}

/**
  * Compute GCD using subtraction method.
  * Subtracts the smaller from the larger until register y is zero.
  * value in register x is then the GCD
  */
class GCD extends Module {
  val io = IO(new Bundle {
    val value1        = Input(UInt(16.W))
    val value2        = Input(UInt(16.W))
    val loadingValues = Input(Bool())
    val outputGCD     = Output(UInt(16.W))
    val outputValid   = Output(Bool())
  })

  val x  = Reg(UInt())
  val y  = Reg(UInt())

  val swap = Module(new BlackBoxSwap)

  when(x > y) { x := x - y }
    .otherwise { y := y - x }

  when(io.loadingValues) {
    //x := io.value1
    //y := io.value2
    swap.io.in1 := io.value1
    swap.io.in2 := io.value2

    x := swap.io.out1
    y := swap.io.out2
  }

  io.outputGCD := x
  io.outputValid := y === 0.U
}

我检查了生成的RTL，看起来是正确的。你能帮个忙吗？非常感谢!

Answer 1

在我看来，您正在尝试使用带有verilog黑盒的firrtl解释器后端。verilog黑盒只能用于基于verilog的后端，如verilator或VCS。如果你不清楚如何设置后端，可以在chisel-template中查找示例。

有一种方法可以通过firrtl解释器后端使用黑盒模拟，但这需要您编写黑盒的scala实现。

Answer 2

Chisel3有几个后端，每个后端都生成自己的输出。Chisel 3.1有默认的后端踏板，所以如果你需要整合你的Verilog，请执行以下操作：

sbt“测试:运行主gcd.GCDMain --is-verbose --后端名称验证器”