GHDL的VCD输出中缺少信号

Question

我正在尝试VHDL书中的一个简单的案例问题。正如您可以从源代码中理解的那样，它根据输入范围设置输出值。但是，当我使用GHDL运行测试平台时，我无法观察到我的输入x。

这是因为x是character类型吗？我应该在GHDL问题页面(https://github.com/ghdl/ghdl/issues)上提问吗？

源代码(q4_case.vhd)：

entity q4_case is

  port (
    x               : in  character;    -- input
    character_class : out integer);     -- output

end entity q4_case;

architecture behav of q4_case is

begin  -- architecture behav

  -- purpose: set output depending on range of input
  -- type   : combinational
  -- inputs : x
  -- outputs: character_class
  process (x) is
  begin  -- process
    case x is
      when 'A' to 'z'       => character_class <= 1;
      when '0' to '9'       => character_class <= 2;
      when nul to usp | del => character_class <= 4;
      when others           => character_class <= 3;
    end case;
  end process;


end architecture behav;

测试平台(q4_case_tb.vhd)：

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity q4_case_tb is

end entity q4_case_tb;

-------------------------------------------------------------------------------

architecture q4_case_tb of q4_case_tb is

  -- component ports
  signal x               : character;
  signal character_class : integer;

  -- clock
  signal Clk : std_logic := '1';

begin  -- architecture q4_case_tb

  -- component instantiation
  DUT : entity work.q4_case
    port map (
      x               => x,
      character_class => character_class);

  -- clock generation
  Clk <= not Clk after 10 ns;

  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here

    x <= 'b';
    wait until Clk = '1';
    wait until Clk = '0';

    x <= 'F';
    wait until Clk = '1';
    wait until Clk = '0';

    x <= dc3;
    wait until Clk = '1';
    wait until Clk = '0';

    x <= usp;
    wait until Clk = '1';
    wait until Clk = '0';

    x <= del;
    wait until Clk = '1';
    wait until Clk = '0';

    x <= '0';
    wait until Clk = '1';
    wait until Clk = '0';

    x <= '5';
    wait until Clk = '1';
    wait until Clk = '0';

    x <= '9';
    wait until Clk = '1';
    wait until Clk = '0';

    x <= '=';
    wait until Clk = '1';
    wait until Clk = '0';

    x <= 'Ü';
    wait until Clk = '1';
    wait until Clk = '0';


    report "End of simulation" severity failure;

  end process WaveGen_Proc;



end architecture q4_case_tb;

-------------------------------------------------------------------------------

configuration q4_case_tb_q4_case_tb_cfg of q4_case_tb is
  for q4_case_tb
  end for;
end q4_case_tb_q4_case_tb_cfg;

-------------------------------------------------------------------------------

编译和运行命令：

ghdl -a q4_case.vhd

ghdl -a q4_case_tb.vhd

ghdl -r q4_case_tb --vcd=q4_case.vcd

版本信息：

ghdl -v
GHDL 0.35 (tarball) [Dunoon edition]
 Compiled with GNAT Version: GPL 2017 (20170515-63)
 mcode code generator
Written by Tristan Gingold.

Copyright (C) 2003 - 2015 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

VCD输出文件的开头如下所示。正如您所看到的，x没有被处理，我不能通过使用GTKWave查看来观察x。

VCD的一部分：

$date
  Thu Feb 08 09:19:40 2018
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$comment x is not handled $end
$var integer 32 ! character_class $end
$var reg 1 " clk $end
$scope module dut $end
$comment x is not handled $end
$var integer 32 # character_class $end
$upscope $end
$enddefinitions $end
#0
b1 !
1"
b1 #
#10000000
...
...

Answer 1

我认为你的问题不在于硬件描述语言本身，而在于它使用Verilog VCD format来记录波形的事实。维基百科的那个页面上说

1996年，

标准1364-1995与Verilog硬件描述语言一起定义了标准的四值VCD格式。

这四个值是0、1、X和Z。

Answer 2

这是我的错，我没有正确地检查GHDL文档。正如在https://ghdl.readthedocs.io/en/latest/using/Simulation.html上写的那样(马修指出)，VCD格式只支持来自std.standard的bit和bit_vector。用VCD文件无法观察到character类型的信号。

正如Brain建议的那样，从VCD转换到GHW格式解决了这个问题。在这种情况下，GKTWave显示的GHW文件没有任何问题。