Quartus2V13.0SP1 DE1board硬件描述语言
我是一名大学生。
教授说“不要使用时钟和事件”。
昨天我在7segmentLED上做了反向开关。
今天我编辑了这个问题很多东西。
Code1下面是正确的行为。
我想在Code2上做这件事,没有“事件”。
--Code1
library IEEE;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all;
entity increase is
port(
key0 : in std_logic;
hex3 : out std_logic_vector(6 downto 0));
end increase;
architecture RTL of increase is
signal hex3c : integer range 0 to 9;
begin
process(key0, hex3c)begin
if(key0' event and key0 = '0') then
if(hex3c = 9) then
hex3c <= 0;
else
hex3c <= hex3c + 1;
end if;
end if;
end process;
process(hex3c)
begin
case hex3c is
when 0 => hex3 <= "1000000";
when 1 => hex3 <= "1111001";
when 2 => hex3 <= "0100100";
when 3 => hex3 <= "0110000";
when 4 => hex3 <= "0011001";
when 5 => hex3 <= "0010010";
when 6 => hex3 <= "0000010";
when 7 => hex3 <= "1111000";
when 8 => hex3 <= "0000000";
when others => hex3 <= "0010000";
end case;
end process;
end RTL;和
--Code2
library IEEE;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all;
entity increase is
port(
key0 : in std_logic;
hex3 : out std_logic_vector(6 downto 0));
end increase;
architecture RTL of increase is
signal hex3c : integer range 0 to 9;
signal prev : std_logic;
begin
process(key0, hex3c, prev)begin
if(key0 = '0' and prev = '0')then
if(hex3c = 9) then
hex3c <= 0;
prev <= '1';
else
hex3c <= hex3c + 1;
prev <= '1';
end if;
elsif(key0 = '1' and prev = '1')then
prev <= '0';
end if;
end process;
process(hex3c)
begin
case hex3c is
when 0 => hex3 <= "1000000";
when 1 => hex3 <= "1111001";
when 2 => hex3 <= "0100100";
when 3 => hex3 <= "0110000";
when 4 => hex3 <= "0011001";
when 5 => hex3 <= "0010010";
when 6 => hex3 <= "0000010";
when 7 => hex3 <= "1111000";
when 8 => hex3 <= "0000000";
when others => hex3 <= "0010000";
end case;
end process;
end RTL;请告诉我如何解决这个问题。
我们真的可以实现这一点吗?
发布于 2016-05-23 15:49:17
我现在还没有评估板来测试你的代码,但现在唯一对我来说可能是问题的是你的敏感性列表。试着把count放进去,这样你的显示就会在它改变时随时更新。
我可以给你的另一个建议是把所有可能的案例--即。当你使用组合过程时,在你的过程中添加else语句。
如果它改变了什么,就让我来吧。
https://stackoverflow.com/questions/37383747
复制相似问题