位序列检测器计数器不工作(VHDL)

Question

我构建了一个具有16位输入的4位序列检测器。我现在想知道序列在16位中出现的频率。

为此，我使用以下代码：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY seqdec IS
PORT    (   X:      IN      std_logic_vector(15 DOWNTO 0);
            CLK:    IN      std_logic;
            RESET:IN        std_logic;
            LOAD:   IN      std_logic;
            Y:      OUT std_logic);
END seqdec;

ARCHITECTURE SEQ OF seqdec IS
TYPE        statetype IS (s0, s1, s2, s3, s4);
SIGNAL  state, next_state: statetype;
SIGNAL  counter: std_logic_vector(3 DOWNTO 0) :="0000" ;
SIGNAL  temp:   std_logic_vector(15 DOWNTO 0);
SIGNAL  so:     std_logic;

    BEGIN
    STATE_AKT: PROCESS (CLK, RESET)
        BEGIN   
            IF RESET = '1' THEN     
                state <= s0 ;
                counter <= (OTHERS => '0') ;
            ELSIF CLK = '1' AND CLK'event THEN
                state <= next_state ;
            END IF;
        END PROCESS STATE_AKT;

    PISO:       PROCESS (CLK, LOAD, X)
        BEGIN
            IF (LOAD = '1') THEN
                temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
            ELSIF (CLK'event and CLK='1') THEN
                so <= temp(15) ;
                temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
                temp(0) <= '0';
            END IF;
        END PROCESS PISO;



    STATE_CAL: PROCESS (so,state)
        BEGIN
            CASE state IS
                WHEN s0 =>  IF so = '0' THEN next_state <= s0  ;
                                ELSE next_state <= s1 ;
                                END IF;
                WHEN s1 =>  IF so = '0' THEN next_state <= s1;
                                ELSE next_state <= s2 ;
                                END IF;
                WHEN s2 =>  IF so = '0' THEN next_state <= s3 ;
                                ELSE next_state <= s2 ;
                                END IF;
                WHEN s3 =>  IF so = '0' THEN next_state <= s0 ;
                                ELSE next_state <= s4 ;
                                END IF;
                WHEN s4 =>  IF so = '0' THEN next_state <= s0;
                                ELSE next_state <= s2 ;
                                END IF;
                WHEN OTHERS => NULL;
            END CASE;
        END PROCESS STATE_CAL;

    STATE_Y: PROCESS (state)
        BEGIN
            CASE state IS
                WHEN s4 =>      
                    Y <= '1'; 
                    counter <= counter + '1';
                WHEN OTHERS =>  Y <= '0' ;
            END CASE;
        END PROCESS STATE_Y;
END SEQ;

但是我的计数器复位和我的计数器增量都不起作用。其余的都运行得很好。

有没有人给我一个提示或点子？

Answer 1

这个程序现在在ModelSim中工作得很好，但我很难把它放到板子上。

我在ModelSim中用不同的参数对它进行了多次模拟，它工作得很好，所以功能部分也很好。

我的代码现在是这样的：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY seqdec IS
PORT    (   X:          IN      std_logic_vector(15 DOWNTO 0);
            CLK:        IN      std_logic;
            RESET:  IN      std_logic;
            LOAD:       IN      std_logic;
            DIGIT:  OUT std_logic_vector(6 DOWNTO 0) := "1111110";
            COUT:       OUT std_logic_vector(2 DOWNTO 0);
            Y:          OUT std_logic);
END seqdec;

ARCHITECTURE SEQ OF seqdec IS
TYPE        statetype IS (s0, s1, s2, s3, s4);
SIGNAL  state: statetype;
SIGNAL  next_state: statetype:=s0;
SIGNAL  counter: std_logic_vector(2 DOWNTO 0) :="000" ;
SIGNAL  temp:   std_logic_vector(15 DOWNTO 0);
SIGNAL  so:     std_logic := 'U';

-------------------Aktualisierung des Zustandes--------------------------------
    BEGIN
    STATE_AKT: PROCESS (CLK, RESET)
        BEGIN   
            IF RESET = '1' THEN     
                state <= s0;
            ELSIF CLK = '1' AND CLK'event THEN
                state <= next_state ;
            END IF;
        END PROCESS STATE_AKT;

---------------------Counter---------------------------------------------------
    COUNT:  PROCESS (state, RESET)
        BEGIN   
            IF (RESET = '1') THEN   
                counter <= (OTHERS => '0');
            ELSIF (state = s4) THEN
                counter <= counter + '1';
                COUT <= counter;
            END IF;
    END PROCESS COUNT;

-------------------PiSo für die Eingabe des zu Prüfenden Vektors---------------
    PISO:       PROCESS (CLK, LOAD, X)
        BEGIN
            IF (LOAD = '1') THEN
                temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
            ELSIF (CLK'event and CLK='1') THEN
                so <= temp(15);
                temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
                temp(0) <= '0';
            END IF;
        END PROCESS PISO;

-------------------Zustandsabfrage und Berechnung------------------------------
    STATE_CAL: PROCESS (so,state)
        BEGIN
            CASE state IS
                WHEN s0 =>  IF so = '0' THEN next_state <= s0  ;
                                ELSIF (so = '1') THEN next_state <= s1 ;
                                END IF;
                WHEN s1 =>  IF so = '0' THEN next_state <= s1;
                                ELSIF (so = '1') THEN next_state <= s2 ;
                                END IF;
                WHEN s2 =>  IF so = '0' THEN next_state <= s3 ;
                                ELSIF (so = '1') THEN next_state <= s2 ;
                                END IF;
                WHEN s3 =>  IF so = '0' THEN next_state <= s0 ;
                                ELSIF (so = '1') THEN next_state <= s4 ;
                                END IF;
                WHEN s4 =>  IF so = '0' THEN next_state <= s0;
                                ELSIF (so = '1') THEN next_state <= s2 ;
                                END IF;
                WHEN OTHERS => NULL;
            END CASE;
        END PROCESS STATE_CAL;

-------------------Ausgang-----------------------------------------------------
    STATE_Y: PROCESS (state)
        BEGIN
            CASE state IS
                WHEN s4 =>      
                    Y <= '1'; 
                WHEN OTHERS =>  Y <= '0' ;
            END CASE;
        END PROCESS STATE_Y;

-------------------7 Segment---------------------------------------------------
    SEVEN_SEG: PROCESS (counter, CLK)
        BEGIN
            IF (RESET = '1') THEN
                DIGIT <= "1111110";
            END IF;
            CASE counter IS
                WHEN "000" => DIGIT <= "1111110";
                WHEN "001" => DIGIT <= "0110000";
                WHEN "010" => DIGIT <= "1101101";
                WHEN "011" => DIGIT <= "1111001";
                WHEN "100" => DIGIT <= "0110011";
                WHEN "101" => DIGIT <= "1011011";
                WHEN OTHERS => NULL;
            END CASE;
        END PROCESS SEVEN_SEG;


END SEQ;

当我把它放在黑板上时，7段会显示一个"3“。我会假设，由于功能部分看起来很好，它必须对时间进行一些思考，但我找不到任何解决方案。如果一些经验的VHDL程序员可以给我一个新的提示，那将是伟大的。

向禤浩焯致以最良好的问候