Verilog Testbench时钟

Question

我已经尝试了多种方法，现在我有点绝望了。我试着在我的测试平台中设置这个时钟，问题出在模拟中，它不工作，或者我的模拟似乎冻结了。我知道一定是闹钟的问题。

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
    end
end
initial begin 
    reset = 0; 
    #15 L = 0; R = 0; H = 0;        
    #20 L = 0; R = 0; H = 1;
    #25 L = 0; R = 1; H = 0;
    #30 L = 0; R = 1; H = 1;
    #35 L = 1; R = 0; H = 0;
    #45 L = 1; R = 0; H = 1;
    #50 L = 1; R = 1; H = 0;
    #55 L = 1; R = 1; H = 1;

    reset = 1; 
    #60 L = 0; R = 0; H = 0;        
    #65 L = 0; R = 0; H = 1;
    #70 L = 0; R = 1; H = 0;
    #75 L = 0; R = 1; H = 1;
    #80 L = 1; R = 0; H = 0;
    #85 L = 1; R = 0; H = 1;
    #90 L = 1; R = 1; H = 0;
    #95 L = 1; R = 1; H = 1;
    $stop ; 
 end 

endmodule模块

Answer 1

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
 end end

尝试将clk=0移到永远循环的上方。不是每#10个单位切换时钟，而是每#10个单位将时钟重置为0，然后立即切换。我认为这在某些情况下可能仍然有效，但这可能不是您想要做的。

Answer 2

对于时钟，只需使用

parameter PERIOD = 10; //whatever period you want, it will be based on your timescale

always #PERIOD clk=~clk; //now you create your cyclic clock

//==//

更完整：

module testbench;
timeunit 1ns;
timeprecision 100ps;
initial begin
  $display($time, " << Starting the Simulation >>");
    rstn = 1'b0;
    clk = 0;
    #5 rstn = 1'b1;
end

always #PERIOD clk=~clk;


initial
begin
      $dumpfile("your_choice_of_name.vcd");
      $dumpvars;
end

initial
begin
//whatever you come up
end

endmodule

Answer 3

或者干脆这样做..

 initial begin 
        reset = 0; clk = 0;
        #15 L = 0; R = 0; H = 0;        
        #20 L = 0; R = 0; H = 1;
        #25 L = 0; R = 1; H = 0;
        #30 L = 0; R = 1; H = 1;
        #35 L = 1; R = 0; H = 0;
        #45 L = 1; R = 0; H = 1;
        #50 L = 1; R = 1; H = 0;
        #55 L = 1; R = 1; H = 1;

        reset = 1; 
        #60 L = 0; R = 0; H = 0;        
        #65 L = 0; R = 0; H = 1;
        #70 L = 0; R = 1; H = 0;
        #75 L = 0; R = 1; H = 1;
        #80 L = 1; R = 0; H = 0;
        #85 L = 1; R = 0; H = 1;
        #90 L = 1; R = 1; H = 0;
        #95 L = 1; R = 1; H = 1;
        $stop ; 
     end 

always 
   #10 clk = ~clk;