移位每个时钟事件，时钟=1 ( VHDL)

Question

这段代码在每个clk'event and clk=1上移位n1和n2，条件是sh=1和su=0。问题是，移位发生在第一个上升沿，而不会再次发生在下一个上升沿，谁知道如何让它连续移动？谢谢。

ENTITY register_divider IS
  port( st , clk :in std_logic ; 
    num : in std_logic_vector (15 downto 0);

    qu : out std_logic_vector(7 downto 0);
    re : out std_logic_vector (7 downto 0);
    n1r : out std_logic_vector ( 8 downto 0 );
    counter : in std_logic_vector ( 3 downto 0);
    Sh, su, Ld: in std_logic ;
    n1c: in std_logic_vector ( 8 downto 0 )
  );
END ENTITY register_divider;

--
ARCHITECTURE rtl OF register_divider IS
BEGIN  

    process(clk)
        variable n1 : std_logic_vector ( 8 downto 0);
        variable n2 : std_logic_vector ( 7 downto 0) ;
    begin

        n2 := num(7 downto 0);
        n1 := '0' & num(15 downto 8); 

        if (clk'event and clk = '1' ) then
             n1r <= n1 ; 
             if ( sh='1' and su = '0') then 
                n1 := n1(7 downto 0) & n2(7);
                n2 := n2(6 downto 0) & '0';
             end if ;

             if  ( su = '1' and su = '1') then 
                n2(0) := '1';
                n1 := n1c ;
             end if ; 
        end if ; 

        qu <= n2 ;
        re <= n1(7 downto 0);
    end process;
 END ARCHITECTURE rtl;

Answer 1

正如mentioned by Brian所说，您的代码正在按您希望的方式移动，然而，问题是它也会在每个周期加载/设置寄存器，本质上会破坏您想要的东西。您不需要在每个周期(无条件)加载/设置寄存器n1和n2，而是需要包含一个条件，以便在断言适当的信号时加载它们(也许是Ld？)