测试平台和代码验证(VHDL)

Question

我是个VHDL新手。我写了一个递减计数器的代码，其中计数器从数组中挑选整数，并将其倒计时到零，然后递增检查输出。我要你们验证代码在逻辑上是否正确。如果是，那么我如何使用测试台来测试它。

entity counter is
   port(clk   : in bit;
        check : out integer);
end counter;     

architecture imp of counter is
   type my_array is array(natural range<>) of integer;
   constant set:my_array(1 to 5):= (2,4,6,8,10);--array of 5 integers
   signal count:integer:=set(1); --initiating count with integer at first location of array 
   signal t : integer;
begin
   process(clk)
      variable i : integer:= 1;--to be used to indicate the locations of array 
   begin
      if (clk='1' and clk'event) and (count>0) then
         count<=count-1;
      elsif (clk='1' and clk'event) and (i<5) then 
         i:=i+1;
         count<= set(i);
         t<=t+1;
      end if;
   end process;
   check<=t;
end imp;

Answer 1

您的代码可以正确编译，但我们需要更详细地说明它应该做些什么，以确保它是正确的。正如@tsukuyo所说，您还需要为第10行中的信号't‘分配一个初始值。

在你修复了这个问题之后，下面是一个测试平台，它会自动测试你的电路并检查输出值。检查测试工作台中的输出值非常重要，因为这样您就不需要在每次更改代码时都盯着波形。由于测试平台是自我检查的，当出现问题时，它会自动告诉您：

use std.textio.all;                                                      
use std.env.all;                                                         

entity counter_tb is                                                     
end;                                                                     

architecture testbench of counter_tb is                                  
   signal clk: bit;                                                      
   signal check: integer;                                                

begin                                                                    
   -- instantiate the unit under test                                    
   uut: entity work.counter port map(clk => clk, check => check);

   -- generate a clock pulse with a 20 ns period                         
   clk <= not clk after 10 ns;                                           

   run_tests: process is                                                 
      -- declare an array with all expected output values                
      type integer_vector is array(natural range<>) of integer;          
      constant EXPECTED_RESULTS: integer_vector := (                     
         0, 0, 0,                                                        
         1, 1, 1, 1, 1,                                                  
         2, 2, 2, 2, 2, 2, 2,                                            
         3, 3, 3, 3, 3, 3, 3, 3, 3,                                      
         4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4                                 
      );                                                                 
      variable log_line: line;                                           

   begin                                                                 
      -- loop through all expected values and ensure that                
      -- they match the actual output value                              
      for i in EXPECTED_RESULTS'range loop                               
         wait until rising_edge(clk);                                    
         write(log_line,                                                 
            "i: " & to_string(i) &                                       
            ", check: " & to_string(check) &                             
            ", expected: " & to_string(EXPECTED_RESULTS(i))              
         );                                                              
         writeline(output, log_line);                                    
         assert check = EXPECTED_RESULTS(i);                             
      end loop;                                                          

      report "End of simulation. All tests passed.";                    
      finish;                                                            
   end process;                                                          

end;       

这是它生成的输出的一个示例：

# Loading std.standard
# Loading std.textio(body)
# Loading std.env(body)
# Loading work.counter_tb(testbench)
# Loading work.counter(imp)
# run -all
# i: 0, check: 0, expected: 0
# i: 1, check: 0, expected: 0
# i: 2, check: 0, expected: 0
# i: 3, check: 1, expected: 1
# i: 4, check: 1, expected: 1
# i: 5, check: 1, expected: 1
# i: 6, check: 1, expected: 1
# i: 7, check: 1, expected: 1
# i: 8, check: 2, expected: 2
# i: 9, check: 2, expected: 2
# i: 10, check: 2, expected: 2
# i: 11, check: 2, expected: 2
# i: 12, check: 2, expected: 2
# i: 13, check: 2, expected: 2
# i: 14, check: 2, expected: 2
# i: 15, check: 3, expected: 3
# i: 16, check: 3, expected: 3
# i: 17, check: 3, expected: 3
# i: 18, check: 3, expected: 3
# i: 19, check: 3, expected: 3
# i: 20, check: 3, expected: 3
# i: 21, check: 3, expected: 3
# i: 22, check: 3, expected: 3
# i: 23, check: 3, expected: 3
# i: 24, check: 4, expected: 4
# i: 25, check: 4, expected: 4
# i: 26, check: 4, expected: 4
# i: 27, check: 4, expected: 4
# i: 28, check: 4, expected: 4
# i: 29, check: 4, expected: 4
# i: 30, check: 4, expected: 4
# i: 31, check: 4, expected: 4
# i: 32, check: 4, expected: 4
# i: 33, check: 4, expected: 4
# i: 34, check: 4, expected: 4
# ** Note:  End of simulation. All tests passed.
#    Time: 690 ns  Iteration: 0  Instance: /counter_tb                                                              

注意:要使用Modelsim运行上述模拟，请键入：

vlib work
vcom -2008 *.vhd
vsim -c counter_tb(testbench) -do "run -all; quit"

Answer 2

代码没有问题，但您需要将初始化值设置为t以进行模拟。

参见Test Benches Overview了解如何使用VHDL语言编写测试平台。

下面是一个简单的例子：

entity counter_tb is
end;

architecture arch of counter_tb is

   component counter is
      port (clk   : in bit;
            check : out integer);
   end component;

   signal clk: bit;
   signal check: integer;
begin

   UUT: counter
      port map (clk => clk, check => check);

   clk_proc: process
   begin
      clk <= '0';
      wait for 50 ns;
      clk <= '1';
      wait for 50 ns;
   end process; 

end arch;