Vivado: TCL命令，将clock1和clock2之间的计时路径设置为假路径(计时-6和计时-7)

Question

假设我有一个FPGA/VHDL设计，它有两个时钟域，一个时钟域到另一个时钟域之间的每个路径都有用VHDL编写的CDC同步代码，以确保在跨越时钟边界之间传递信息时不存在亚稳定。

在这种情况下，将clock1和clock2之间的定时路径设置为clock1和clock2之间的每个定时路径的假路径的Vivado TCL命令是什么？

示例编译器警告：

WARNING: [TIMING-6] The clocks clk_1 and clk_2 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_out1_design_zynq_zyboz720_clk_wiz_0_0] 

WARNING: [TIMING-7] The clocks clk_1 and clk_2 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_1] -to [get_clocks clk_2]

Answer 1

set_false_path -from [get_clocks clk_1] -to [get_clocks clk_2]

此命令将删除与此CDC相关的警告和预期的关键警告“时间未满足”，但这不能确保您的设计将正常工作。

我建议您在重新同步信号上也添加属性ASYNC_REG，以确保合成器会将2个CDC FF放在非常接近的位置(如果可能，在同一个切片中)：

attribute ASYNC_REG : string;
attribute ASYNC_REG of a_r_clk_2  : signal is "TRUE"; -- Output of the first resync FF in clk_2
attribute ASYNC_REG of a_rr_clk_2 : signal is "TRUE"; -- Output of the second resync FF in clk_2