Verilog中的sign extender不关心吗？

Question

代码：

module signextend(input wire [15:0] inputVal, output wire [31:0] outputVal);
        assign outputVal = {{16{inputVal[15]}}, inputVal};
endmodule

测试平台：

module lastname_SignExt;

    reg [15:0] input1;
    wire [31:0] output1;

    signextend mySignExt(input1, output1);

    initial begin

        #350
        $dumpfile("lastname_SignExt.vcd");
        $dumpvars(350, lastname_SignExt);
        $display("***********Sign Extender Test***********\n");

        input1 = 16'b0000000000000110;
        $display("input1 %16b extended: output1 %32b", input1,output1);
        //if(output1  == 32'hFFFF1000)
        //    $display("Sign Extender Test 1 Passed, Input was %d and Ouput is %d!\n", input1, output1); 
        //else 
        //    $display("Sign Extender Test 1 Failed!\n");
        
        // #50
        // input1 = 16'h0001;
        // if(output1  == 32'h00000001)
        //     $display("Sign Extender Test 1 Passed, Input was %d and Ouput is %d!\n", input1, output1); 
        // else 
        //     $display("Sign Extender Test 2 Failed!\n");
        
        $finish;
    end
endmodule

输出：

VCD info: dumpfile lastname_SignExt.vcd opened for output.
***********Sign Extender Test***********

input1 0000000000000110 extended: output1 xxxxxxxxxxxxxxxx0000000000000110

Answer 1

当我在$display之前添加延迟时，在output1中看不到未知位(x

    input1 = 16'b0000000000000110;
    #1;
    $display("input1 %16b extended: output1 %32b", input1,output1);

输出：

***********Sign Extender Test***********

input1 0000000000000110 extended: output1 00000000000000000000000000000110

最好是在信号值稳定时使用$display，而不是在信号值发生变化时使用。