错误问题(vlog-2110)对网络的非法引用

Question

我正在编写一个SystemVerilog赋值来模拟一个逻辑电路，结果出现了以下错误。我不明白该怎么处理它。请帮帮忙。

以下是错误消息：

** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "C".

这是我的代码：

module biii (input logic A,B,C,
output logic F);
assign F = ~(~(A & C) & (B & ~(C)));
endmodule

module t_1c(input logic A,B,C,
output logic F);
biii B2(A,B,C,F);

initial begin

#20
A=0;B=0;C=0;
#20
A=0;B=1;C=0;
#20
A=0;B=0;C=1;
#20
A=1;B=1;C=0;
#20
A=1;B=0;C=0;
#20
A=0;B=1;C=0;
#20;
end
endmodule

Answer 1

t_1c模块看起来像一个测试台。在这种情况下，您不需要将信号声明为模块端口。这些错误意味着您不能对模块内声明为input端口的信号进行赋值。更改：

module t_1c(input logic A,B,C,
output logic F);

至：

module t_1c;

logic A,B,C,F;