vlog-7错误。在读取模式下打开设计单元文件失败

Question

我试图使用英特尔提供的tcl脚本运行IntelFPGA的示例设计。它报告了在读模式下打开单元文件"blabla“的错误(vlog-7)。没有这样的文件或目录(errno = ENOENT)。我找不到错误。然后我尝试了我以前使用过的一个modelsim项目，它曾经工作过。我得到了同样的错误！有什么问题吗？

在tb_run.tcl开始时(从命令行MODELSIM> VHDL 2008 do tb_run.tcl运行)，这个tb_run.tcl文件是由quartus示例生成的

global env ;

# set QUARTUS_INSTALL_DIR "$env(QUARTUS_ROOTDIR)" => initially i thought
# there is something wrong with the rootdir, so i changed to the row 
# below:
set QUARTUS_INSTALL_DIR "C:/intelFPGA/18.0/quartus"
set SETUP_SCRIPTS ../setup_scripts
set tb_top_waveform msim_wave.do
set QSYS_SIMDIR "./../setup_scripts"

set TOP_LEVEL_NAME tb_top

source $SETUP_SCRIPTS/mentor/msim_setup.tcl

# Compile device library files

dev_com 

================================================ => dev_com，这是第29行，这里发生错误，请参阅下面

modelsim报告：

Modelsim> VHDL 2008 do tb_run.tcl
# C:/intelFPGA/18.0/quartus
# ../setup_scripts
# msim_wave.do
# ./../setup_scripts
# tb_top
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
# 
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
# [exec] dev_com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 10:43:14 on Jun 25,2019
# vlog -reportprogress 300 C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver 
# ** Error: (vlog-7) Failed to open design unit file "C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 10:43:14 on Jun 25,2019, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
# Error in macro ./tb_run.tcl line 29
# C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
#     while executing
# "vlog C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver"
#     ("eval" body line 1)
#     invoked from within
# "eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"             ..."
#     invoked from within
# "if [string is false -strict [modelsim_ae_select $FORCE_MODELSIM_AE_SELECTION]] {
#     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_CO..."
#     ("eval" body line 5)
#     invoked from within
# "dev_com "

Answer 1

我真的不知道你是如何通过重启来解决这个问题的。以下是最有可能发生的问题，以及我是如何解决的。

我们有一个关于这个问题的声明：vlog-7错误。在读取模式中打开设计单元文件失败

我太专注于“读取模式”，试图弄明白为什么禁止开始声明的操作。但是，最有可能的问题是，在出现警告的目录中，您实际上没有实际的文件。

然后，我意识到我最终更改了文件夹的名称，因此无法读取该文件。看一看，直到你的tcl、.do和项目文件，你才会在文件中做任何修改。