MIPS流水线的EX_MEM锁存

Question

我正在实现MIPS体系结构的流水线，并且在执行模块和内存模块之间的锁存中存在过度使用。

这是我现在的代码：

module ex_mem(
input wire [1:0] ctlwb_out,
input wire [2:0] ctlm_out,
input wire [31:0] adder_out,
input wire aluzero,
input wire [31:0] aluout, readdat2,
input wire [4:0] muxout,
output reg [1:0] wb_ctlout,
output reg branch, memread, memwrite,
output reg [31:0] add_result,
output reg zero,
output reg [31:0] alu_result, rdata2out,
output reg [4:0] five_bit_muxout
);

initial begin
    wb_ctlout <= 0; 
    branch <= 0; 
    memread <= 0; 
    memwrite <= 0;
    add_result <= 0;
    zero <= 0;
    alu_result <= 0; 
    rdata2out <= 0;
    five_bit_muxout <= 0;
end

always @ * begin
#1 //delay


wb_ctlout <= ctlwb_out;
branch <= ctlm_out[2]; //unsure   ] 
memread <= ctlm_out[1]; //unsure  ] -- of correct order
memwrite <= ctlm_out[0]; //unsure ]
add_result <= adder_out;   
zero <= aluzero;
alu_result <= aluout;
rdata2out <= readdat2;
five_bit_muxout <= muxout;
end

endmodule

我得到的错误是：

地点30-58 IO安置是不可行的。未放置终端(107)的数目大于可用站点(100)的数目。以下组I/O终端容量不足: IO组:0 with : SioStd: LVCMOS18 VCCO = 1.8终端:0 TermDir: Out RangeId: 1 Drv: 12设备上只有100个可用站点，但需要107个站点。任期: add_result条件: add_result1条件: add_result2条件: add_result3条件: add_result4条件: add_result5条件: add_result6条件:add_result6条件: add_result8条件: add_result9条件: add_result10条件: add_result12条件:添加_result13项: add_result14项: add_result15项: add_result16项: add_result17项: add_result18项: add_result19项: add_result20项: add_result21项: add_result22项: add_result23项: add_result24项: add_result25项: add_result26项任期: add_result27条件: add_result28条件: add_result29条件: add_result30条件: add_result31条件: alu_result条件: alu_result1条件: alu_result2条件: alu_result3条件: alu_result4条件: alu_result5条件: alu_result6条件: alu_result7条件：：alu_result8术语: alu_result9术语: alu_result10术语: alu_result11术语: alu_result12术语: alu_result13条件: alu_result14条件: alu_result15条件: alu_result16条件: alu_result17条件: alu_result18条件: alu_result19条件: alu_result20条件: alu_result21项: alu_result22项: alu_result23项: alu_result24项: alu_result25项: alu_result26项: alu_result27项: alu_result28项: alu_result29项: alu_result30项: alu_result31项: rdata2out项: rdata2out1项: rdata2out2项: rdata2out3项任期: rdata2out4条件: rdata2out6条件:rdata2out6条件: rdata2out8条件:rdata2out8条件: rdata2out10条件:rdata2out10条件: rdata2out11条件: rdata2out12条件: rdata2out13条件: rdata2out15条件: rdata2out16条件: rdata2out17条件: rdata2out18条件: rdata2out20条件任期: rdata2out21条件: rdata2out22条件: rdata2out23条件: rdata2out24条件: rdata2out25条件: rdata2out26条件: rdata2out27条件: rdata2out28条件: rdata2out29条件: rdata2out30条件: five_bit_muxout条件: five_bit_muxout1条件: five_bit_muxout2条件: five_bit_muxout3术语: five_bit_muxout4术语: wb_ctlout术语: wb_ctlout1术语:分支术语: memread术语:mem书面术语:零

有人能帮忙吗？谢谢。

Answer 1

module ex_mem(
input wire [1:0] ctlwb_out,
input wire [2:0] ctlm_out,
input wire [31:0] adder_out,
input wire aluzero,
input wire [31:0] aluout, readdat2,
input wire [4:0] muxout,
output reg [1:0] wb_ctlout,
output reg branch, memread, memwrite,
output reg [31:0] add_result,
output reg zero,
output reg [31:0] alu_result, rdata2out,
output reg [4:0] five_bit_muxout
);





always @ * begin
// #1 //delay
wb_ctlout = 0; 
branch = 0; 
memread = 0; 
memwrite = 0;
add_result = 0;
zero = 0;
alu_result = 0; 
rdata2out = 0;
five_bit_muxout = 0;

wb_ctlout = ctlwb_out;
branch = ctlm_out[2]; //unsure   ] 
memread = ctlm_out[1]; //unsure  ] -- of correct order
memwrite = ctlm_out[0]; //unsure ]
add_result = adder_out;   
zero = aluzero;
alu_result = aluout;
rdata2out = readdat2;
five_bit_muxout = muxout;
end

endmodule

组合逻辑使用阻塞分配。

延迟不是合成的东西

不要对默认值使用初始值，而是使用reset或如代码所示。