参数化长度的Verilog移位寄存器

Question

我是Verilog代码的新手。我必须用移位寄存器在verilog代码中做一个问题。我在问之前搜索了一下，但没有找到类似的东西。有人能帮我在Verilog中为这个寄存器创建代码吗？

谢谢!祝您今天愉快!

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Answer 1

也许这会让你：

module DW03_shft_reg #(
// the parameterisable length of the shift register needs to be a parameter
    parameter LENGTH = 1              
  )(
      input [LENGTH-1:0] p_in,
      input s_in, load_n, shift_n, clk, 
      // this needs to be a 'reg' so that it can be assigned to by the 'always' block
      output reg [LENGTH-1:0] p_out     
  );

    // the template for sequential code with no asynchronous reset
    always @(posedge clk)               
        begin
          // implement the behaviour from the truth table here
          // the { , } (concatenation) operator is useful for shift registers
        end

endmodule