模型error Altera误差

Question

我使用的是UbuntuLinux14.04LTS和Altera 15.0网络版，由于授权错误，我很难模拟我的设计。我正在为LCD_driver设计一个韦克-MT液晶触摸屏，由terasic设计，旋流器IV型EP4CE115由Altera设计。

老实说，我对像ModelSim-Altera这样的仿真软件没有多少经验，但我知道如何使用.vwf文件并使用它们进行仿真，我也知道如何使用信号分析逻辑分析器。在创建了应用程序.vwf文件之后，我编译了该项目，我按下run functional 并获得了一个窗口，其内容如下：

确定ModelSim可执行文件的位置..。 使用: /home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin 若要指定ModelSim可执行目录，请选择: Tools -> Options -> EDA工具选项注意:如果ModelSim和ModelSim可执行文件都可用，则将使用ModelSim。 生成ModelSim测试平台* ld.so: dl-clse.c: 762：_dl_close: Assertion map->l\_init\_called' failed! Info: \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Sun Aug 9 22:18:46 2015Info: Command: quartus\_eda --gen\_testbench --check\_outputs=on --tool=modelsim\_oem --format=verilog --write\_settings\_files=off test5 -c test5 --vector\_source=/path/to/Altera/projects/test/5/test5.vwf --testbench\_file=/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vtWarning (201007): Can't find port "h\_counter" in designWarning (201007): Can't find port "h\_counter[10]" in designWarning (201007): Can't find port "h\_counter[9]" in designWarning (201007): Can't find port "h\_counter[8]" in designWarning (201007): Can't find port "h\_counter[7]" in designWarning (201007): Can't find port "h\_counter[6]" in designWarning (201007): Can't find port "h\_counter[5]" in designWarning (201007): Can't find port "h\_counter[4]" in designWarning (201007): Can't find port "h\_counter[3]" in designWarning (201007): Can't find port "h\_counter[2]" in designWarning (201007): Can't find port "h\_counter[1]" in designWarning (201007): Can't find port "h\_counter[0]" in designWarning (201007): Can't find port "v\_counter" in designWarning (201007): Can't find port "v\_counter[9]" in designWarning (201007): Can't find port "v\_counter[8]" in designWarning (201007): Can't find port "v\_counter[7]" in designWarning (201007): Can't find port "v\_counter[6]" in designWarning (201007): Can't find port "v\_counter[5]" in designWarning (201007): Can't find port "v\_counter[4]" in designWarning (201007): Can't find port "v\_counter[3]" in designWarning (201007): Can't find port "v\_counter[2]" in designWarning (201007): Can't find port "v\_counter[1]" in designWarning (201007): Can't find port "v\_counter[0]" in designWarning (201007): Can't find port "HSD\_s" in designWarning (201007): Can't find port "VSD\_s" in designInfo (201000): Generated Verilog Test Bench File /path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt for simulationInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 25 warnings Info: Peak virtual memory: 1088 megabytes Info: Processing ended: Sun Aug 9 22:18:47 2015 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. Completed successfully. \*\*\*\* Generating the functional simulation netlist \*\*\*\* quartus\_eda --write\_settings\_files=off --functional=on --flatten\_buses=off --simulation --tool=modelsim\_oem --format=verilog --output\_directory="/path/to/Altera/projects/test/5/simulation/qsim/" test5 -c test5 Inconsistency detected by ld.so: dl-close.c: 762: \_dl\_close: Assertionmap->l_init_called‘failed！信息：*******************************************************************Info:运行Quartus II 64位EDA Netlist Writer Info:版本15.0.0构建14504/22/2015 SJ信息:版权(C) 1991-2015年Altera公司。版权所有。信息:您使用Altera公司的设计工具、逻辑功能信息和其他软件和工具，以及它的AMPP合作伙伴逻辑信息: functions和任何来自上述信息(包括设备编程或模拟文件)的输出文件，以及任何信息:相关文档或信息都明确显示为主题信息: Altera程序许可证信息的条款和条件:订阅协议，Altera Quartus II许可证协议， 信息: Altera MegaCore功能许可协议，或其他 信息:适用的许可协议，包括，但不限于， 信息:您的使用仅用于编程逻辑。 信息: Altera公司生产的设备，由Altera公司或其 信息:授权分销商。请参阅适用的 信息:关于进一步细节的协议。信息:已开始处理: Sun 8月9日22:18:53 2015Info:命令: quartus_eda --写设置_quartus_eda=off-functional=on-flatten_ was =off-模拟=on-tool=modelsim_oem-format=verilog test5 -c test5Info (204019)：EDA模拟toolInfo: Quartus II 64位中生成的文件test5.vo是成功的。0错误，0警告信息:峰值虚拟内存: 1093兆字节信息:处理结束: Sun Aug 9 22:18:55 2015 Info:运行时间: 00:00:02 Info:总CPU时间(在所有处理器上)：00:00:01成功完成。 生成ModelSim .do脚本* /path/to/Altera/projects/test/5/simulation/qsim/test5.do生成。 顺利完成。 运行ModelSim模拟* /home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/vsim -c -do test5.do 加载共享库时出现/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/../linux/vish:错误: libXft.so.2:无法打开共享对象文件:没有此类文件或目录错误。

任何帮助都是非常感谢的。

Answer 1

尤里卡!我搜索了以下文本：error while loading shared libraries: libXft.so.2: cannot open shared object file: No such file or directory Error.，我发现(感谢秋 )，我需要为我的64位操作系统安装32位软件包，这是ModelSim软件使用的。下面是进入Ubuntu终端的正确命令：

sudo apt-get install libxft2 libxft2:i386 lib32ncurses5

问题解决了！