基于$monitor的verilog仿真

Question

我一直试图在Verilog实现全加器。我已经实施了它，它也显示了Isim的结果。唯一的问题是，当我尝试使用$monitor命令查看仿真时，它只显示了一个结果，而不是所有的模拟结果。下面是testbench代码：

module Full_adder_s2_testbench;

// Inputs
reg a;
reg b;
reg cin;

// Outputs
wire sum;
wire cout;

// Instantiate the Unit Under Test (UUT)
Full_adder_s2 uut (
    .a(a), 
    .b(b), 
    .cin(cin), 
    .sum(sum), 
    .cout(cout)
);
integer i;

initial begin
    // Initialize Inputs
    a = 0;
    b = 0;
    cin = 0;

    // Wait 100 ns for global reset to finish
    #100;

    end
    always @ ( a, b, cin )
            begin

            // generate truth table
            for ( i = 0; i < 8; i = i + 1 )
                    // every 10 ns set a, b, and cin to the binary rep. of i
                    #10 {a, b, cin} = i;
                    $monitor( "%d ns: a + b + cin = %b + %b + %b = cout sum = %b %b",
                                             $time, a, b, cin, cout, sum );  
            // stop 10ns after last change of inputs
            #10 $stop;
            end


endmodule

ISIM的结果是：

# run 1000 ns 
Simulator is doing circuit initialization process.

Finished circuit initialization process.

                 400 ns: a + b + cin = 1 + 1 + 1 = cout sum = 1 1

Stopped at time : 410 ns :  in File "E:/Namal/FYP/My work/XILINX/Full_adder_s2/Full_adder_s2_testbench.v" Line 66 

Answer 1

$monitor只需要设置一次，每次发生信号更改时都会触发，请尝试使用$display，因为always @*中已经有了语句。

在学习Verilog的同时，我鼓励您自由地使用begin end。问题是，for循环中只有1行，$display/$monitor在外部，因此在开始时只执行一次。

always @* begin
  // generate truth table
  for ( i = 0; i < 8; i = i + 1 ) begin //<-- Added begin
    // every 10 ns set a, b, and cin to the binary rep. of i
    #10 {a, b, cin} = i;
    $display( "%d ns: a + b + cin = %b + %b + %b = cout sum = %b %b", $time, a, b, cin, cout, sum ); 
  end //<--Added end
  // stop 10ns after last input
  #10 $stop;

结束

EDA游乐场上的完整示例。

注意:最好不要再使用手动灵敏度列表，用always @ ( a, b, cin )替换always @*。这将导致更快的重构和降低RTL的机会门模拟错配。