blocks|key|957055|text|Verilog-A和Verilog是相关的，但非常不同。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|957056|Verilog是首先标准化的，通常用于描述数字电路和测试台的行为。Verilog是事件驱动的。模拟行为可以在测试台中模拟，但模拟行为的建模可能是困难的。|957057|Verilog-a后来被标准化了，并且基于verilog的语法.它用于模拟电路的建模。这两种语言不兼容，都有另一种不支持的结构。Verilog-a可以模拟连续的时间行为，如spice/幽灵模拟器。它不能很好地模拟数字行为。Modelsim或其他“Verilog模拟器”不支持Verilog-a+-它主要由spice模拟器支持。|957058|Verilog是Verilog的一种进化，它允许模拟和数字结构在同一个文件/块中共存。然而，它同样只支持现代verilog的一个子集。它不受标准Verilog模拟器的支持--同样，支持更多的是模拟/spice/频谱模拟器。|957059|entityMap^0|0|0|0|0^^$0|@$1|2|3|4|5|6|7|J|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|K|8|@]|9|@]|A|$]]|$1|D|3|E|5|6|7|L|8|@]|9|@]|A|$]]|$1|F|3|G|5|6|7|M|8|@]|9|@]|A|$]]|$1|H|3|-4|5|6|7|N|8|@]|9|@]|A|$]]]|I|$]]

Verilog-A and Verilog are related but very different.

Verilog was standardized first and is usually for describing the behaviour of digital circuits and testbenches. Verilog is event driven. Analog behaviour can be simulated in testbenches, but modelling of analog behavior can be difficult.

Verilog-a was standardized later, and was based on the syntax of verilog. It is intended for the modelling of analog circuits. The two languages are not compatible, both having constructs that the other does not support. Verilog-a can simulate continuous time behaviour, like spice/spectre simulators.
It does not model digital behaviour very well.
Modelsim, or other 'Verilog simulators' do not support Verilog-a - it is mostly supported by spice simulators.

Verilog-AMS is an evolution of Verilog-a, which allows both analog and digital constructs to co-exist in the same file/block. However, it again only supports a subset of modern verilog. It is not supported by the standard Verilog simulators - again support is more on the analog/spice/spectre simulators.

blocks|key|957021|text|Verilog源自IEEE+1364+Verilog+HDL规范，但它们并不相同。|type|ordered-list-item|depth|inlineStyleRanges|entityRanges|data|957022|我认为this问题可以帮助你找到你想要的东西。|offset|length|957023|unstyled|957024|957025|entityMap|0|LINK|mutability|MUTABLE|url|https://electronics.stackexchange.com/questions/35208/free-veriloga-simulators^0|0|3|4|0|0|0|0^^$0|@$1|2|3|4|5|6|7|Q|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|R|8|@]|9|@$D|S|E|T|1|U]]|A|$]]|$1|F|3|-4|5|G|7|V|8|@]|9|@]|A|$]]|$1|H|3|-4|5|G|7|W|8|@]|9|@]|A|$]]|$1|I|3|-4|5|G|7|X|8|@]|9|@]|A|$]]]|J|$K|$5|L|M|N|A|$O|P]]]]

<ol>
<li>Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification, but they aren't the same.</li>
<li>I think that <a href="https://electronics.stackexchange.com/questions/35208/free-veriloga-simulators">this</a> question can help you find what you are looking for.</li>
</ol>

blocks|key|957083|text|Verilog是一个被废弃的数字硬件描述标准。形式上，最后的版本是IEEE+1364-2005。它已经被SystemVerilog+(IEEE1807-2017)所取代。虽然受到反对，但许多工具仍然支持它。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|957084|Verilog是一个模拟扩展.与其数字语言不同，该语言仅用于验证(仿真)，不能被合成。它由“开放的Verilog国际”行业协会标准化。后来，该标准成为Verilog(Verilog的模拟和混合信号扩展)的一个子集。|957085|如果你想模拟Verilog，你需要一个合适的模拟器.这可以是一个混合信号模拟器(例如VCS、Questa或Allegro+)。或者，大多数商业香料模拟器支持Verilog。|957086|entityMap^0|0|0|0^^$0|@$1|2|3|4|5|6|7|H|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|I|8|@]|9|@]|A|$]]|$1|D|3|E|5|6|7|J|8|@]|9|@]|A|$]]|$1|F|3|-4|5|6|7|K|8|@]|9|@]|A|$]]]|G|$]]

Verilog is a deprecated standard for digital hardware description. Formally that last version was IEEE 1364-2005. It has been superseded by SystemVerilog (IEEE 1800-2017). Though deprecated, many tools still support it.

Verilog-A is an analog extension. Unlike its digital counterpart, the language is only for verification (simulation), it cannot be synthesized. It was standardized by the "Open Verilog International" trade association. Later the standard was incorporated as a subset of Verilog-AMS (analog and mixed signal extensions to Verilog).

If you want to simulate Verilog-A you will need a suitable simulator. This could be a mixed signal simulator (VCS AMS, Questa ADMS or Allegro AMS for instance). Alternatively most commercial SPICE simulators support Verilog-A.

blocks|key|957113|text|Verilog-A和Verilog不一样。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|957114|用Verilog描述数字电路，用Verilog对模拟电路的行为进行建模。|957115|Verilog运行在事件驱动的模拟器上，而Verilog需要一个连续的时间，类似香料的模拟器.|957116|事件驱动模拟器比连续时间模拟器快几个数量级，因为与后者不同，事件驱动模拟器不需要计算每个电路节点的电压和电流。信号被抽象为1和0，只有当驱动程序更新时才触发网络评估。|957117|我不知道支持Verilog和/或Verilog(混合信号味道或Verilog)的免费模拟器。|957118|另一方面，验证器是(数字)+verilog仿真的一个很好的选择。它还支持一些verilog的构造，如wreal。|957119|entityMap^0|0|0|0|0|0|0^^$0|@$1|2|3|4|5|6|7|N|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|O|8|@]|9|@]|A|$]]|$1|D|3|E|5|6|7|P|8|@]|9|@]|A|$]]|$1|F|3|G|5|6|7|Q|8|@]|9|@]|A|$]]|$1|H|3|I|5|6|7|R|8|@]|9|@]|A|$]]|$1|J|3|K|5|6|7|S|8|@]|9|@]|A|$]]|$1|L|3|-4|5|6|7|T|8|@]|9|@]|A|$]]]|M|$]]

Verilog-A is not the same as Verilog.
Verilog is used to describe digital circuits whereas Verilog-A is used to model the behavior of analog circuits.
Verilog runs on event-driven simulators whereas Verilog-A requires a continuous time, spice-like simulator.
Event-driven simulators are orders of magnitude faster than continuous time simulators because, as opposed to the latter, event-driven simulators don't require the computation of voltages and currents for each and every circuit node. Signals are abstracted as 1 and 0s and net evaluation is triggered only when the driver is updated.
I am not aware of free simulators supporting Verilog-A and/or Verilog-AMS (the mixed-signal flavor or Verilog)
On the other hand, verilator is a great choice for (digital) verilog simulation. It also supports some constructs of verilog-ams such as wreal.

<ul>
<li>Is Verilog-A the same as Verilog ?</li>
<li>Is there a testing compiler for Verilog-A? </li>
</ul>

Because when I just paste some sources code of Verilog-A on ModelSim, there are always some errors that can't be removed. Can ModelSim run Verilog-A?

Verilog-A & Verilog ; Are they the same?

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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Verilog-A和Verilog一样吗？有Verilog的测试编译器吗？因为当我在ModelSim上粘贴一些Verilog的源代码时，总会有一些不能删除的错误。ModelSim能运行Verilog吗？

问Verilog &A&Verilog；它们是一样的吗？
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