FSM未按预期工作(序列检测器0110)

Question

我不知道下面的代码有什么问题。只有在适当调整仿真延迟后，它才能给我输出1。它给了我一个接一个不同的序列。我反复检查了我的逻辑好几次。请帮我找到我的虫子。

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码

module seq_0110(sequence_in,clock,reset,detector_out
    );
input clock; 
input reset; 
input sequence_in; 
output reg detector_out; 
reg [1:0] current_state, next_state; // current state and next state


always @(posedge clock, posedge reset)
begin
 if(reset==1) 
 current_state <=2'b00;// when reset=1, reset the state of the FSM to "Zero" State
 else
 current_state <= next_state; // otherwise, next state
end 

always @(current_state,sequence_in)
begin
 case(current_state) 
 2'b00:begin
  if(sequence_in==1)
   next_state <= 2'b00;
  else
   next_state <= 2'b01;
 end
 2'b01:begin
  if(sequence_in==1)
   next_state <= 2'b10;
  else
   next_state <= 2'b01;
 end
 2'b10:begin
  if(sequence_in==1)
   next_state <= 2'b11;
  else
   next_state <= 2'b01;
 end 
 2'b11:begin
  if(sequence_in==1)
   next_state <= 2'b00;
  else
   next_state <= 2'b01;
 end
 
 default:next_state <= 2'b00;
 endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin 
 case(current_state) 
 2'b00:   detector_out <= 1'b0;
 2'b01:   detector_out <=1'b0;
 2'b10:  detector_out <= 1'b0;
 2'b11:  detector_out <=(sequence_in==1)?1'b0:1'b1;
 
 default:  detector_out <= 1'b0;
 endcase
end 
endmodule

Answer 1

问题在于您的测试平台以及如何在日志文件中显示信号。

在您在your other Question earlier today中发布的testbench代码中，您使用$monitor打印输入和输出信号。问题是，$monitor只在两个信号发生变化时才显示这些信号。在你的例子中，每个时钟周期只显示一次这些信号就更有意义了。这可以使用always块和$display来完成，如下所示：

always @(negedge clock) $display($time, " in=%b out=%b", sequence_in, detector_out);

initial begin
  $dumpfile("seq_0110.vcd");
  $dumpvars(0,seq_0110_t);
  sequence_in = 0;
  reset = 1;
  #30;
  reset = 0;

  repeat (5) @(posedge clock); sequence_in = 0;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 0;

  repeat (5) @(posedge clock); sequence_in = 0;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 0;

  repeat (5) @(posedge clock); sequence_in = 0;

  #10 $finish;
end

现在，输出清楚地显示，FSM检测到输入上的0110位模式：

          10 in=0 out=0
          20 in=0 out=0
          30 in=0 out=0
          40 in=0 out=0
          50 in=0 out=0
          60 in=0 out=0
          70 in=0 out=0
          80 in=0 out=0
          90 in=1 out=0
         100 in=1 out=0
         110 in=0 out=1
         120 in=0 out=0
         130 in=0 out=0
         140 in=0 out=0
         150 in=0 out=0
         160 in=0 out=0
         170 in=1 out=0
         180 in=1 out=0
         190 in=0 out=1
         200 in=0 out=0
         210 in=0 out=0
         220 in=0 out=0
         230 in=0 out=0
         240 in=0 out=0