使用Verilog创建一个4状态Mealy有限状态机[帮助]

Question

我想弄清楚如何在没有任何错误的情况下运行它。

module main;
(
    input wire clk, reset;
    input wire x, y;
    output reg n, c;
    s0 = 0,
    s1 = 1,
    s2 = 2,
    s3 = 3;
    
    state_reg; 
    state_next; 
);
always(posedge clk, posedge reset)
begin
    if (reset) begin
        state_reg = s0;
    end
    else begin
        state_reg = state_next;
    end
end 

always (x, y, state_reg) begin 
    state_next = state_reg; 
    n = 0;
    c = 0;
    case (state_reg)
        s0 : begin
            if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 0;
                state_next = s1; 
            end
        end
        s1 : begin
              if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 0;
                state_next = s2; 
            end
        end
        s2 : begin
              if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 1;
                state_next = s3; 
            end
        end
        s3 : begin
             if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 1;
                state_next = s3; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 1;
                state_next = s3; 
            end
        end
    endcase
endmodule

我觉得这段代码应该显示出我想要做的事情，但如果没有，我还附上了逻辑原理图版本的图片(由于我是新的，所以我不知道如何在这个网站上附加原理图的.cct文件)。对不起，伙计们，这是我第一次使用Verilog，所以我对此非常陌生，但我必须为一个零指导的荣誉项目写这个。因此，如果我输入x或y(0或1 )，它应该根据条件(s0、s1、s2、s3等)切换到不同的状态。如果我点击了reset，它应该返回到s0，如果我点击clk或时钟变量，它应该使用输入x和y来决定下一个状态应该是什么。

编辑:这是我得到的错误。

jdoodle.v:2: syntax error
jdoodle.v:3: error: invalid module item.
jdoodle.v:6: syntax error
jdoodle.v:6: error: Invalid module instantiation
jdoodle.v:11: error: Invalid module instantiation
jdoodle.v:12: error: Invalid module instantiation
jdoodle.v:13: error: invalid module item.
jdoodle.v:14: syntax error
jdoodle.v:17: Syntax in assignment statement l-value.
jdoodle.v:18: syntax error
jdoodle.v:20: error: invalid module item.
jdoodle.v:21: syntax error
jdoodle.v:25: error: invalid module item.
jdoodle.v:26: syntax error
jdoodle.v:26: error: Invalid module instantiation
jdoodle.v:27: error: Invalid module instantiation
jdoodle.v:31: syntax error
jdoodle.v:31: error: Invalid module instantiation
jdoodle.v:32: error: Invalid module instantiation
jdoodle.v:33: error: Invalid module instantiation
jdoodle.v:36: syntax error
jdoodle.v:36: error: Invalid module instantiation
jdoodle.v:37: error: Invalid module instantiation
jdoodle.v:38: error: Invalid module instantiation
jdoodle.v:41: syntax error
jdoodle.v:41: error: Invalid module instantiation
jdoodle.v:42: error: Invalid module instantiation
jdoodle.v:43: error: Invalid module instantiation
jdoodle.v:46: syntax error
jdoodle.v:46: error: Invalid module instantiation
jdoodle.v:47: error: Invalid module instantiation
jdoodle.v:48: error: Invalid module instantiation
jdoodle.v:53: syntax error
jdoodle.v:53: error: Invalid module instantiation
jdoodle.v:54: error: Invalid module instantiation
jdoodle.v:55: error: Invalid module instantiation
jdoodle.v:58: syntax error
jdoodle.v:58: error: Invalid module instantiation
jdoodle.v:59: error: Invalid module instantiation
jdoodle.v:60: error: Invalid module instantiation
jdoodle.v:63: syntax error
jdoodle.v:63: error: Invalid module instantiation
jdoodle.v:64: error: Invalid module instantiation
jdoodle.v:65: error: Invalid module instantiation
jdoodle.v:68: syntax error
jdoodle.v:68: error: Invalid module instantiation
jdoodle.v:69: error: Invalid module instantiation
jdoodle.v:70: error: Invalid module instantiation
jdoodle.v:75: syntax error
jdoodle.v:75: error: Invalid module instantiation
jdoodle.v:76: error: Invalid module instantiation
jdoodle.v:77: error: Invalid module instantiation
jdoodle.v:80: syntax error
jdoodle.v:80: error: Invalid module instantiation
jdoodle.v:81: error: Invalid module instantiation
jdoodle.v:82: error: Invalid module instantiation
jdoodle.v:85: syntax error
jdoodle.v:85: error: Invalid module instantiation
jdoodle.v:86: error: Invalid module instantiation
jdoodle.v:87: error: Invalid module instantiation
jdoodle.v:90: syntax error
jdoodle.v:90: error: Invalid module instantiation
jdoodle.v:91: error: Invalid module instantiation
jdoodle.v:92: error: Invalid module instantiation
jdoodle.v:97: syntax error
jdoodle.v:97: error: Invalid module instantiation
jdoodle.v:98: error: Invalid module instantiation
jdoodle.v:99: error: Invalid module instantiation
jdoodle.v:102: syntax error
jdoodle.v:102: error: Invalid module instantiation
jdoodle.v:103: error: Invalid module instantiation
jdoodle.v:104: error: Invalid module instantiation
jdoodle.v:107: syntax error
jdoodle.v:107: error: Invalid module instantiation
jdoodle.v:108: error: Invalid module instantiation
jdoodle.v:109: error: Invalid module instantiation
jdoodle.v:112: syntax error
jdoodle.v:112: error: Invalid module instantiation
jdoodle.v:113: error: Invalid module instantiation
jdoodle.v:114: error: Invalid module instantiation

Answer 1

有几个语法错误阻止了这个模块的编译。

在模块名‘’之后的分号是IO列表中的语法(模块名之后是错误，需要是逗号。要声明状态变量的

• 是IO列表区域(就在word模块之后)。这是个错误。将声明放在IO列表之后。

搜索'verilog状态机‘以了解如何和在何处声明状态变量。

• 您需要非阻塞赋值(<=)，而不是始终块中带有时钟的非阻塞分配(=)。

• 您的总是块缺少定时控制操作符@。在模块末尾缺少' end’关键字的

• 。状态机

• 没有:默认状态，这可能导致一些奇怪的行为。

f 215

我做了这些更改(没有添加一个默认状态，因为它将修改您的设计意图)。

下面是您现在在edaplayground.com上使用Mentor编译的代码--您没有发布一个testbench，无法知道它是否以您希望的方式运行。

搜索‘基本的verilog测试平台’，开始一个测试平台的设计。

module main
(
    input wire clk, 
    input wire reset,
    input wire x,
    input wire y,
    output reg n,
    output reg c
);
  
localparam   
    s0 = 2'b00,
    s1 = 2'b01,
    s2 = 2'b10,
    s3 = 2'b11;
    
reg [1:0] state_reg,state_next; 
  
always @(posedge clk, posedge reset)
begin
    if (reset) begin
        state_reg <= s0;
    end
    else begin
        state_reg <= state_next;
    end
end 

always @(x, y, state_reg) begin 
    state_next = state_reg; 
    n = 0;
    c = 0;
    case (state_reg)
        s0 : begin
            if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 0;
                state_next = s1; 
            end
        end
        s1 : begin
              if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 0;
                state_next = s2; 
            end
        end
        s2 : begin
              if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 1;
                state_next = s3; 
            end
        end
        s3 : begin
             if (x == 0 && y == 0) begin
                n = 0;
                c = 0;
                state_next = s0;
            end
            else if (x == 0 && y == 1) begin
                n = 0;
                c = 0;
                state_next = s0; 
            end
            else if (x== 1 && y == 0) begin
                n = 0;
                c = 1;
                state_next = s3; 
            end
             else if (x== 1 && y == 1) begin
                n = 1;
                c = 1;
                state_next = s3; 
            end
        end
    endcase
  
end
  
endmodule