#interrupt-cells为2，但interrupts为3元组

Question

我查看了Beagle Bone Black的设备树，并从am57xx-beagle-x15.dts开始。深入dra7.dtsi我发现了gpio1

gpio1: gpio@4ae10000 {
            compatible = "ti,omap4-gpio";
            reg = <0x4ae10000 0x200>;
            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
            ti,hwmods = "gpio1";
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };

我读到过#interrupt-cells给出了u32s列表中某一项所需的interrupts或单元格的数量。但是当我查看interrupts时，我看到了一个3元组：<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>。我很想知道，为什么这里包含3个单元格，而不是2个？

Answer 1

这是一个非常晚的答案，但请添加一个，以便有人可以获得帮助。

我无法从当前的Linux5.15源代码中找到确切的dts文件。但是节点的interrupt-parent应该需要3个单元用于interrupts属性。对于gic，通常需要3个值-{中断类型，中断编号，标志}。在Linux5.15的gic (Documentation/devicetree/bindings/interrupt-controller/arm，gic.yaml的设备绑定文档中)

  "#interrupt-cells":
    const: 3
    description: |
      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
      interrupts.

      The 2nd cell contains the interrupt number for the interrupt type.
      SPI interrupts are in the range [0-987].  PPI interrupts are in the
      range [0-15].

      The 3rd cell is the flags, encoded as follows:
        bits[3:0] trigger type and level flags.
          1 = low-to-high edge triggered
          2 = high-to-low edge triggered (invalid for SPIs)
          4 = active high level-sensitive
          8 = active low level-sensitive (invalid for SPIs).
        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
        Also note that the configurability of PPI interrupts is IMPLEMENTATION
        DEFINED and as such not guaranteed to be present (most SoC available
        in 2014 seem to ignore the setting of this flag and use the hardware
        default value).