尝试使用Verilog时出现解析错误；测试LFSR不起作用

Question

我目前正在使用Verilog进行随机数生成。消息来源表明，使用线性反馈移位寄存器是随机化MSB的最佳方法之一。所以我决定对LFSR进行编码和测试。代码片段如下：

module lfsr_counter(clk, reset, ce, lfsr_done);

input clk, reset, ce;
output lfsr_done;

reg lfsr_done;
reg [10:0] lfsr;
initial lfsr_done = 0;
wire d0,lfsr_equal;

xnor(d0,lfsr[10],lfsr[8]);
assign lfsr_equal = (lfsr == 11'h359);

always @(posedge clk,posedge reset) begin
    if(reset) begin
        lfsr <= 0;
        lfsr_done <= 0;
    end
    else begin
        if(ce)
          lfsr <= lfsr_equal ? 11'h0 : {lfsr[9:0],d0};
          lfsr_done <= lfsr_equal;
    end
end
endmodule


module testbench();

reg clk, reset, ce;
wire lfsr_done;

lfsr_counter dut(clk, reset, ce, lfsr_done); // Design Under Test

initial
begin

    reset = 0;
        clk = 1;
    ce = 0;

        #100
    ce = 1;
        #200 $finish;
end

//Generate Clock
always #10 clk = !clk; 

endmodule

但是我一直收到这些解析错误：

​

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我真的不明白。我正在使用Verilogger Pro btw

Answer 1

我认为块术语总是用or分隔，而不是逗号。

always @(posedge clk or posedge reset) begin