我应该如何在Verilog中重置我的重置信号？

Question

我有两个always模块，一个用来计数已通过的能够异步复位的时钟周期数，另一个用来在某些输入信号的负沿触发复位信号。

always@(posedge clock or posedge reset)

begin: ClockCounter

if(reset == 1)
    begin
    clock_cnt = 1;  
    end
else
    begin
    clock_cnt = clock_cnt + 1;
    end
end

always@(negedge pulse_in)

begin: Receiver

negedge_cnt = negedge_cnt + 1;

reset = 1;

.......Code goes on

end
end module

我想要做的是，一旦clock_cnt复位到1，就将复位信号设为0，这样它就可以在下一个时钟周期中继续计数。如果我尝试在clock_cnt =1之后插入reset = 0；，我会遇到多个驱动器连接到同一信号的问题。有谁知道怎么做吗？

Answer 1

除非有真正重要的原因，并且您已经保证了无故障的组合逻辑，否则您不应该使用异步重置来清除寄存器。典型的方法是使用同步清除信号，而不是使用异步复位。

下面是代码的样子：

always @(posedge clk or posedge reset) begin
  if (reset) begin // Note that you need to separate the asynchronous reset and synchronous clear logic (ie, dont do 'if (reset | clr)') 
    counter <= 1; // Use non-blocking assignment for clocked blocks
  end
  else begin
    if (clr) begin
      counter <= 1;
    end
    else begin
      counter <= counter + 1;
    end
  end
end

always @(posedge clk) begin // You need to synchronize your input pulse, Im assuming its synchronous to your clock, otherwise youll need a synchronizer
  if (prev_pulse_in & ~pulse_in) begin
    negedge_cnt <= negedge_cnt + 1;
    clr <= 1;
  end
  else begin
    clr <= 0;
  end
  prev_pulse_in <= pulse_in;
end

Answer 2

我的解决方案是

always@(posedge clock or posedge reset)

begin: ClockCounter

if(reset == 1)
    begin
    clock_cnt = 1;
    reset_flag = 1;
    end
else
    begin
    clock_cnt = clock_cnt + 1;
    reset_flag = 0;
    end
end

always@(negedge pulse_in or posedge reset_flag)
begin

reset = 1;

if(reset_flag == 1)
reset = 0;
end