尝试从Verilog写入文本文件，但输出文件为空

Question

我需要在一个文件中一个接一个地写两个来自Verilog模块的变量。在单周期信号freq_rdy的上升沿更新变量。我正在使用下面的代码。

integer write_file1;
integer freq_rdy_1,freq_rdy_2;

initial begin

write_file1 = $fopen("frequencies.txt","w");        
freq_rdy_1 = testbench.UUT.read_controller.freq_rdy;
freq_rdy_2 = testbench.UUT.read_controller_2.freq_rdy;
        
@(posedge freq_rdy_1)
    $fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i); 

@(posedge freq_rdy_2)  
    $fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i); 

 
#1000000
$fclose(write_file1);    
end

输出文本文件为空。我在这段代码中做错了什么？

Answer 1

问题是你只在看到freq_rdy_1或freq_rdy_2的posedge时才写入文件，但是，你永远不会得到这些信号的posedge，因为你只设置了一次(在@posedge语句之前)。因此，您永远不会向文件中写入任何内容。

也许这就是你要找的：

integer write_file1;
initial begin
    write_file1 = $fopen("frequencies.txt","w");
    forever begin
        fork
            begin
                @(posedge testbench.UUT.read_controller.freq_rdy);
                $fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i);
            end
            begin
                @(posedge testbench.UUT.read_controller_2.freq_rdy);
                $fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i);
            end
            begin
                #1_000_000;
                $fclose(write_file1);
            end
        join
    end
end

Answer 2

我能看到波形中的边缘。

通过用a替换w，解决了这个问题。

而不是

$fopen("frequencies.txt","w");

我写了

$fopen("frequencies.txt","a");

虽然我每次运行模拟时都要删除文件。

其余的逻辑是使用always块实现的。

initial begin 
write_file1 = $fopen("frequencies.txt","a");
end 
always @(posedge. testbench.UUT.read_controller.freq_rdy)         begin 
$fwrite(write_file1,"%d \n",testbench.UUT.read_controller.frequency_i);
end 
always @(posedge testbench.UUT.read_controller_2.freq_rdy)       begin 
$fwrite(write_file1,"%d \n",testbench.UUT.read_controller_2.frequency_i); 
end