vhdl: Xilinx代码错误

Question

我们得到这个错误集：

Line 23: Mismatch in number of elements assigned in conditional signal assignment
Line 23: Expression has 1 elements ; expected 7

在此代码中，第23行是

Q_out <= "1111110" when Q_in = "0000" else


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port (
      Q_in  : in  UNSIGNED (3 downto 0);
      Q_out : out  UNSIGNED (6 downto 0)
);
end decoder;
architecture behavioral      of decoder is
begin
Q_out <= "1111110" when Q_in = "0000" else
        "0110000" when Q_in = "0001" else
        "1101101" when Q_in = "0010" else
        "1111001" when Q_in = "0011" else
        "0110011" when Q_in = "0100" else
        "1011011" when Q_in = "0101" else
        "0011111" when Q_in = "0110" else
        "1110000" when Q_in = "0111" else
        "1111111" when Q_in = "1000" else
        "1110011" when Q_in = "1001" else 
        "X";


 end behavioral    ;

Answer 1

VHDL是强类型的，这意味着当你分配信号时，你需要匹配端口宽度和类型。在您的情况下，您不匹配端口宽度，这是错误告诉您的。您正在尝试将1位宽的对象分配给7位宽的对象。尝试：

 "1110011" when Q_in = "1001" else 
 (others => 'X');

在VHDL语言中，others关键字意味着它将填满与端口宽度匹配所需的所有X。